Position innerhalb des Seitenbaumes

Start
Einreichung
Polian, Ilia

Ilia Polian

Herr Prof. Dr. rer. nat. habil.

Institutsleiter und Lehrstuhlinhaber Hardwareorientierte Informatik
Institut für Technische Informatik
Hardwareorientierte Informatik

Kontakt

+49 711 685 60764
+49 711 685 88288
E-Mail

Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Raum: 3.160

Fachgebiet

Research Interests and Activities

Hardware-oriented security: Fault-injection attacks; hardware realizations of postquantum cryptography; hardware Trojans; physical unclonable functions
Robustness: Test methods for nano and microelectronic circuits; defect modeling; power-aware test; test of embedded SRAMs; reliability and functional safety; safety vs. security
Emerging architectures: Stochastic circuits and their use in neuromorphic applications; architectures with memristive components; security aspects of emerging architectures
Quantum computing: Design and validation of advanced quantum error-correcting schemes (topological QEC)

Major Projects

Algebraic Fault Attacks (with Universities of Freiburg and Passau, funded by DFG)
TRUDEVICE: Trustworthy Manufacturing and Utilization of Secure Devices (COST Action IC 1204, 22 involved countries, Vice Speaker)
Test and Diagnosis in Nanoscale Technologies (with University of Freiburg, funded by DFG)
REALTEST: Test and Reliability of Nano-Electronic Systems (with Universities of Stuttgart, Freiburg, Paderborn, Fraunhofer IIS-EAS Dresden, funded by DFG)
EFRE Competence Center for Pervasive Computing and Embedded Systems (in Passau; funded by European Regional Development Fund) – Center's web site (German-only)

Active Ongoing Collaborations

Bernd Becker (University of Freiburg)
Austin Fowler (Google Santa Barbara)
John P. Hayes (University of Michigan, Ann Arbor)
Osnat Keren (Bar Ilan University, Israel)
Martin Kreuzer (University of Passau)
Francesco Regazzoni (USI Lugano)

Publikationen

2024
1. Locking enabled security analysis of cryptographic circuits. Devanshi Upadhyaya; Maël Gay and Ilia Polian. Cryptography 8, 1 (2024).
  - BibTeX
  - Link
  BibTeX
  @article{cryptography8010001, abteilung = {hocos}, author = {Upadhyaya, Devanshi and Gay, Maël and Polian, Ilia}, issn = {2410-387X}, journal = {Cryptography}, number = 1, title = {Locking enabled security analysis of cryptographic circuits.}, url = {https://www.mdpi.com/2410-387X/}, volume = 8, year = 2024 }
  Link
  https://www.mdpi.com/2410-387X/
2. Scenario-based test content optimization: Scan-test vs.~system-level test. Nourhan Elhamawy; Ilia Polian; Jens Anders and Matthias Sauer. In To appear in Proceedings of 42nd IEEE VLSI Test Symposium (VTS), Tempe, AZ, USA, 2024.
  - BibTeX
  BibTeX
  @inproceedings{ElhamPAS_2024, abteilung = {hocos}, author = {Elhamawy, Nourhan and Polian, Ilia and Anders, Jens and Sauer, Matthias}, booktitle = {To appear in Proceedings of 42nd IEEE VLSI Test Symposium (VTS)}, day = {22--24}, location = {Tempe, AZ, USA}, month = {04}, title = {Scenario-based test content optimization: Scan-test vs.~system-level test.}, venue = {Tempe, AZ, USA}, year = 2024 }
2023
1. Cryogenic Embedded System to Support Quantum Computing: From 5nm FinFET to Full Processor. Paul R. Genssler; Florian Klemme; Shivendra Singh Parihar; Sebastian Brandhofer; Girish Pahwa; Ilia Polian; Yogesh Singh Chauhan and Hussam Amrouch. IEEE Transactions on Quantum Engineering (2023). DOI: https://doi.org/10.1109/TQE.2023.3300833
  - BibTeX
  BibTeX
  @article{cryo2023tqe, abteilung = {star hocos}, author = {Genssler, Paul R. and Klemme, Florian and Parihar, Shivendra Singh and Brandhofer, Sebastian and Pahwa, Girish and Polian, Ilia and Chauhan, Yogesh Singh and Amrouch, Hussam}, doi = {10.1109/TQE.2023.3300833}, journal = {IEEE Transactions on Quantum Engineering}, title = {Cryogenic Embedded System to Support Quantum Computing: From 5nm FinFET to Full Processor}, year = 2023 }
2. Review on Resistive Switching Devices Based on Multiferroic BiFeO(3). Xianyue Zhao; Stephan Menzel; Ilia Polian; Heidemarie Schmidt and Nan Du. Nanomaterials (Basel) 13, 8 (April 2023). DOI: https://doi.org/10.3390/nano13081325
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  This review provides a comprehensive examination of the state-of-the-art research on resistive switching (RS) in BiFeO(3) (BFO)-based memristive devices. By exploring possible fabrication techniques for preparing the functional BFO layers in memristive devices, the constructed lattice systems and corresponding crystal types responsible for RS behaviors in BFO-based memristive devices are analyzed. The physical mechanisms underlying RS in BFO-based memristive devices, i.e., ferroelectricity and valence change memory, are thoroughly reviewed, and the impact of various effects such as the doping effect, especially in the BFO layer, is evaluated. Finally, this review provides the applications of BFO devices and discusses the valid criteria for evaluating the energy consumption in RS and potential optimization techniques for memristive devices.
  BibTeX
  @article{Zhao2023-yw, abstract = {This review provides a comprehensive examination of the state-of-the-art research on resistive switching (RS) in BiFeO(3) (BFO)-based memristive devices. By exploring possible fabrication techniques for preparing the functional BFO layers in memristive devices, the constructed lattice systems and corresponding crystal types responsible for RS behaviors in BFO-based memristive devices are analyzed. The physical mechanisms underlying RS in BFO-based memristive devices, i.e., ferroelectricity and valence change memory, are thoroughly reviewed, and the impact of various effects such as the doping effect, especially in the BFO layer, is evaluated. Finally, this review provides the applications of BFO devices and discusses the valid criteria for evaluating the energy consumption in RS and potential optimization techniques for memristive devices.}, abteilung = {hocos}, address = {Switzerland}, author = {Zhao, Xianyue and Menzel, Stephan and Polian, Ilia and Schmidt, Heidemarie and Du, Nan}, doi = {10.3390/nano13081325}, journal = {Nanomaterials (Basel)}, language = {en}, month = {04}, number = 8, title = {Review on Resistive Switching Devices Based on Multiferroic {BiFeO(3})}, volume = 13, year = 2023 }
3. Exploring gate-diversity enabled by reconfigurable memristive technology. Sebastian Brandhofer; Ziang Chen; Li-Wei Chen; Nan Du and Ilia Polian. In To appear in Proceedings of IEEE Int’l Conf. on Electronics, Circuits and Systems (ICECS), Istanbul, Turkey, 2023.
  - BibTeX
  BibTeX
  @inproceedings{BrandCCZDP_2023, abteilung = {hocos}, author = {Brandhofer, Sebastian and Chen, Ziang and Chen, Li-Wei and Du, Nan and Polian, Ilia}, booktitle = {To appear in Proceedings of IEEE Int'l Conf. on Electronics, Circuits and Systems (ICECS)}, day = {4--7}, location = {Istanbul, Turkey}, month = {12}, title = {Exploring gate-diversity enabled by reconfigurable memristive technology}, venue = {Istanbul, Turkey}, year = 2023 }
4. Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing. Lorenzo Masciullo; Roberto Passerone; Francesco Regazzoni and Ilia Polian. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–6. DOI: https://doi.org/10.1109/ETS56758.2023.10174181
  - BibTeX
  BibTeX
  @inproceedings{10174181, abteilung = {hocos}, author = {Masciullo, Lorenzo and Passerone, Roberto and Regazzoni, Francesco and Polian, Ilia}, booktitle = {2023 IEEE European Test Symposium (ETS)}, day = {22--26}, doi = {10.1109/ETS56758.2023.10174181}, location = {Venice, Italy}, month = {05}, pages = {1-6}, title = {Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing}, year = 2023 }
5. Automating Greybox System-Level Test Generation. Denis Schwachhofer; Maik Betka; Steffen Becker; Stefan Wagner; Matthias Sauer and Ilia Polian. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–4. DOI: https://doi.org/10.1109/ETS56758.2023.10173985
  - BibTeX
  BibTeX
  @inproceedings{10173985, abteilung = {hocos}, author = {Schwachhofer, Denis and Betka, Maik and Becker, Steffen and Wagner, Stefan and Sauer, Matthias and Polian, Ilia}, booktitle = {2023 IEEE European Test Symposium (ETS)}, day = {22--26}, doi = {10.1109/ETS56758.2023.10173985}, location = {Venice, Italy}, month = {05}, pages = {1-4}, title = {Automating Greybox System-Level Test Generation}, year = 2023 }
6. Optimal Partitioning of Quantum Circuits Using Gate Cuts and Wire Cuts. Sebastian Brandhofer; Ilia Polian and Kevin Krsulich. IEEE Transactions on Quantum Engineering (2023), pp. 1–10. DOI: https://doi.org/10.1109/TQE.2023.3347106
  - BibTeX
  BibTeX
  @article{10374226, abteilung = {hocos}, author = {Brandhofer, Sebastian and Polian, Ilia and Krsulich, Kevin}, doi = {10.1109/TQE.2023.3347106}, journal = {IEEE Transactions on Quantum Engineering}, pages = {1-10}, title = {Optimal Partitioning of Quantum Circuits Using Gate Cuts and Wire Cuts}, year = 2023 }
7. Stochastic Computing as a Defence Against Adversarial Attacks. Florian Neugebauer; Vivek Vekariya; Ilia Polian and John P. Hayes. In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), Porto, Portugal, 2023, pp. 191–194. DOI: https://doi.org/10.1109/DSN-W58399.2023.00053
  - BibTeX
  BibTeX
  @inproceedings{10207101, abteilung = {hocos}, author = {Neugebauer, Florian and Vekariya, Vivek and Polian, Ilia and Hayes, John P.}, booktitle = {2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, day = {27--30}, doi = {10.1109/DSN-W58399.2023.00053}, location = {Porto, Portugal}, month = {06}, pages = {191-194}, title = {Stochastic Computing as a Defence Against Adversarial Attacks}, year = 2023 }
8. A modular open-source cryptographic co-processor for Internet of Things. Dina Hesse; Maël Gay; Ilia Polian and Elif Bilge Kavun. In To appear in Proceedings of Euromicro Conf. Digital System Design (DSD), Durres, Albania, 2023.
  - BibTeX
  BibTeX
  @inproceedings{HesseGPK_2023, abteilung = {hocos}, author = {Hesse, Dina and Gay, Maël and Polian, Ilia and Kavun, Elif Bilge}, booktitle = {To appear in Proceedings of Euromicro Conf. Digital System Design (DSD)}, day = {6--8}, location = {Durres, Albania}, month = {09}, title = { A modular open-source cryptographic co-processor for Internet of Things}, venue = {Durres, Albania}, year = 2023 }
9. A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. Jens Anders; Pablo Andreu; Bernd Becker; Steffen Becker; Riccardo Cantoro; Nikolaos I. Deligiannis; Nourhan Elhamawy; Tobias Faller; Carles Hernandez; Nele Mentens; Mahnaz Namazi Rizi; Ilia Polian; Abolfazl Sajadi; Mathias Sauer; Denis Schwachhofer; Matteo Sonza Reorda; Todor Stefanov; Ilya Tuzov; Stefan Wagner and Nuša Zidarič. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–10. DOI: https://doi.org/10.1109/ETS56758.2023.10174099
  - BibTeX
  BibTeX
  @inproceedings{10174099, abteilung = {hocos}, author = {Anders, Jens and Andreu, Pablo and Becker, Bernd and Becker, Steffen and Cantoro, Riccardo and Deligiannis, Nikolaos I. and Elhamawy, Nourhan and Faller, Tobias and Hernandez, Carles and Mentens, Nele and Rizi, Mahnaz Namazi and Polian, Ilia and Sajadi, Abolfazl and Sauer, Mathias and Schwachhofer, Denis and Reorda, Matteo Sonza and Stefanov, Todor and Tuzov, Ilya and Wagner, Stefan and Zidarič, Nuša}, booktitle = {2023 IEEE European Test Symposium (ETS)}, day = {22--26}, doi = {10.1109/ETS56758.2023.10174099}, location = {Venice, Italy}, month = {05}, pages = {1-10}, title = {A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors}, year = 2023 }
10. Side-channel Attacks on Memristive Circuits Under External Disturbances. Li-Wei Chen; Xianyue Zhao; Ziang Chen; Nan Du and Ilia Polian. In 2023 IEEE 32nd Asian Test Symposium (ATS), Beijing, China, 2023, pp. 1–6. DOI: https://doi.org/10.1109/ATS59501.2023.10317969
  - BibTeX
  BibTeX
  @inproceedings{10317969, abteilung = {hocos}, author = {Chen, Li-Wei and Zhao, Xianyue and Chen, Ziang and Du, Nan and Polian, Ilia}, booktitle = {2023 IEEE 32nd Asian Test Symposium (ATS)}, day = {14--17}, doi = {10.1109/ATS59501.2023.10317969}, location = {Beijing, China}, month = {10}, pages = {1-6}, title = {Side-channel Attacks on Memristive Circuits Under External Disturbances}, year = 2023 }
11. On Side-Channel Analysis of Memristive Cryptographic Circuits. Li-Wei Chen; Ziang Chen; Werner Schindler; Xianyue Zhao; Heidemarie Schmidt; Nan Du and Ilia Polian. IEEE Transactions on Information Forensics and Security 18, (2023), pp. 463–476. DOI: https://doi.org/10.1109/TIFS.2022.3223232
  - BibTeX
  BibTeX
  @article{9956966, abteilung = {hocos}, author = {Chen, Li-Wei and Chen, Ziang and Schindler, Werner and Zhao, Xianyue and Schmidt, Heidemarie and Du, Nan and Polian, Ilia}, doi = {10.1109/TIFS.2022.3223232}, journal = {IEEE Transactions on Information Forensics and Security}, pages = {463-476}, project = {memcrypto}, title = {On Side-Channel Analysis of Memristive Cryptographic Circuits}, volume = 18, year = 2023 }
12. On the limitations of logic locking the approximate circuits. Karthik Nayak; Devanshi Upadhyaya; Francesco Regazzoni and Ilia Polian. In To appear in Proceedings of IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Singapore, SG, 2023.
  - BibTeX
  BibTeX
  @inproceedings{NayakURP2023, abteilung = {hocos}, author = {Nayak, Karthik and Upadhyaya, Devanshi and Regazzoni, Francesco and Polian, Ilia}, booktitle = {To appear in Proceedings of IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST)}, location = {Singapore, SG}, title = {On the limitations of logic locking the approximate circuits}, venue = {Singapore, SG}, year = 2023 }
13. Overview of Memristive Cryptography. Ilia Polian; Nan Du and Werner Schindler. In 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom, 2023, pp. 1–5. DOI: https://doi.org/10.1109/NEWCAS57931.2023.10198201
  - BibTeX
  BibTeX
  @inproceedings{10198201, abteilung = {hocos}, author = {Polian, Ilia and Du, Nan and Schindler, Werner}, booktitle = {2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)}, day = {26--28}, doi = {10.1109/NEWCAS57931.2023.10198201}, location = {Edinburgh, United Kingdom}, month = {06}, pages = {1-5}, title = {Overview of Memristive Cryptography}, year = 2023 }
14. Optimizing quantum algorithms on bipotent architectures. Yanjun Ji; Kathrin F. Koenig and Ilia Polian. Phys. Rev. A 108, 2 (August 2023), pp. 022610. DOI: https://doi.org/10.1103/PhysRevA.108.022610
  - BibTeX
  - Link
  BibTeX
  @article{PhysRevA.108.022610, abteilung = {hocos}, author = {Ji, Yanjun and Koenig, Kathrin F. and Polian, Ilia}, doi = {10.1103/PhysRevA.108.022610}, journal = {Phys. Rev. A}, month = {08}, number = 2, numpages = {17}, pages = 022610, publisher = {American Physical Society}, title = {Optimizing quantum algorithms on bipotent architectures}, url = {https://link.aps.org/doi/10.1103/PhysRevA.108.022610}, volume = 108, year = 2023 }
  Link
  https://link.aps.org/doi/10.1103/PhysRevA.108.022610
15. Optimal qubit reuse for near-term quantum computers. Sebastian Brandhofer; Ilia Polian and Kevin Krsulich. In To appear in Proceedings Quantum Computing and Engineering Conf.~(QCE), Seattle, Washington, USA, 2023.
  - BibTeX
  BibTeX
  @inproceedings{BrandPK_2023, abteilung = {hocos}, author = {Brandhofer, Sebastian and Polian, Ilia and Krsulich, Kevin}, booktitle = {To appear in Proceedings Quantum Computing and Engineering Conf.~(QCE)}, day = {17--22}, location = {Seattle, Washington, USA}, month = {09}, title = {Optimal qubit reuse for near-term quantum computers. }, venue = {Seattle, Washington, USA}, year = 2023 }
16. LEDA: Locking enabled differential analysis of cryptographic circuits. Devanshi Upadhyaya; Mael Gay and Ilia Polian. In To appear in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, CA, USA, 2023.
  - BibTeX
  BibTeX
  @inproceedings{UpadhGP2022, abteilung = {hocos}, author = {Upadhyaya, Devanshi and Gay, Mael and Polian, Ilia}, booktitle = {To appear in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST)}, day = {1--4}, location = {San Jose, CA, USA,}, month = {05}, title = {LEDA: Locking enabled differential analysis of cryptographic circuits}, venue = {San Jose, CA, USA,}, year = 2023 }
2022
1. Intelligent Methods for Test and Reliability. Hussam Amrouch; Jens Anders; Steffen Becker; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; André van Hoorn; Hanieh Jafarzadeh; Ingmar Kallfass; Florian Klemme; Steffen Koch; Ralf Küsters; Andrés Lalama; Raphael Latty; Yiwen Liao; Natalia Lylina; Zahra Paria Najafi-Haghi; Dirk Pflüger; Ilia Polian; Jochen Rivoir; Matthias Sauer; Denis Schwachhofer; Steffen Templin; Christian Volmer; Stefan Wagner; Daniel Weiskopf; Hans-Joachim Wunderlich; Bin Yang and Martin Zimmermann. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, 2022, pp. 1–6.
  - BibTeX
  BibTeX
  @inproceedings{date2022GS, abteilung = {star,hocos,ra}, author = {Amrouch, Hussam and Anders, Jens and Becker, Steffen and Betka, Maik and Bleher, Gerd and Domanski, Peter and Elhamawy, Nourhan and Ertl, Thomas and Gatzastras, Athanasios and Genssler, Paul R. and Hasler, Sebastian and Heinrich, Martin and Hoorn, André van and Jafarzadeh, Hanieh and Kallfass, Ingmar and Klemme, Florian and Koch, Steffen and Küsters, Ralf and Lalama, Andrés and Latty, Raphael and Liao, Yiwen and Lylina, Natalia and Najafi-Haghi, Zahra Paria and Pflüger, Dirk and Polian, Ilia and Rivoir, Jochen and Sauer, Matthias and Schwachhofer, Denis and Templin, Steffen and Volmer, Christian and Wagner, Stefan and Weiskopf, Daniel and Wunderlich, Hans-Joachim and Yang, Bin and Zimmermann, Martin}, booktitle = {Design, Automation & Test in Europe Conference & Exhibition, DATE 2022}, month = {03}, pages = {1–6}, place = {Antwerp, Belgium}, title = {Intelligent Methods for Test and Reliability}, year = 2022 }
2. Calibration-Aware Transpilation for Variational Quantum Optimization. Yanjun Ji; Sebastian Brandhofer and Ilia Polian. In 2022 IEEE International Conference on Quantum Computing and Engineering (QCE), 2022, pp. 204–214. DOI: https://doi.org/10.1109/QCE53715.2022.00040
  - BibTeX
  BibTeX
  @inproceedings{9951287, abteilung = {hocos}, author = {Ji, Yanjun and Brandhofer, Sebastian and Polian, Ilia}, booktitle = {2022 IEEE International Conference on Quantum Computing and Engineering (QCE)}, doi = {10.1109/QCE53715.2022.00040}, pages = {204-214}, title = {Calibration-Aware Transpilation for Variational Quantum Optimization}, year = 2022 }
3. Human vs. Automatic Detection of Deepfake Videos Over Noisy Channels. Swaroop Shankar Prasad; Ofer Hadar; Thang Vu and Ilia Polian. In 2022 IEEE International Conference on Multimedia and Expo (ICME), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ICME52920.2022.9859954
  - BibTeX
  BibTeX
  @inproceedings{9859954, abteilung = {hocos}, author = {Prasad, Swaroop Shankar and Hadar, Ofer and Vu, Thang and Polian, Ilia}, booktitle = {2022 IEEE International Conference on Multimedia and Expo (ICME)}, doi = {10.1109/ICME52920.2022.9859954}, pages = {1-6}, title = {Human vs. Automatic Detection of Deepfake Videos Over Noisy Channels}, year = 2022 }
4. Benchmarking the performance of portfolio optimization with QAOA. Sebastian Brandhofer; Daniel Braun; Vanessa Dehn; Gerhard Hellstern; Matthias Hüls; Yanjun Ji; Ilia Polian; Amandeep Singh Bhatia and Thomas Wellens. 2022.2022. DOI: https://doi.org/10.48550/ARXIV.2207.10555
  - BibTeX
  BibTeX
  @misc{https://doi.org/10.48550/arxiv.2207.10555, abteilung = {hocos}, author = {Brandhofer, Sebastian and Braun, Daniel and Dehn, Vanessa and Hellstern, Gerhard and Hüls, Matthias and Ji, Yanjun and Polian, Ilia and Bhatia, Amandeep Singh and Wellens, Thomas}, copyright = {Creative Commons Attribution 4.0 International}, doi = {10.48550/ARXIV.2207.10555}, publisher = {arXiv}, title = {Benchmarking the performance of portfolio optimization with {QAOA}}, year = 2022 }
5. Physics inspired compact modelling of BiFe₃ based memristors. Sahitya Yarragolla; Nan Du; Torben Hemke; Xianyue Zhao; Ziang Chen; Ilia Polian and Thomas Mussenbrock. Scientific Reports 12, 1 (November 2022), pp. 20490. DOI: https://doi.org/10.1038/s41598-022-24439-4
  Zusammenfassung
  With the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFe\$\$\backslashmathrmØ\\_\3\\$\$ (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current--voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistant with experimental results.
  BibTeX
  @article{Yarragolla2022, abstract = {With the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFe{\$}{\$}{\backslash}mathrm{\{}O{\}}{\_}{\{}3{\}}{\$}{\$} (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current--voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistant with experimental results.}, abteilung = {hocos}, author = {Yarragolla, Sahitya and Du, Nan and Hemke, Torben and Zhao, Xianyue and Chen, Ziang and Polian, Ilia and Mussenbrock, Thomas}, day = 28, doi = {10.1038/s41598-022-24439-4}, issn = {2045-2322}, journal = {Scientific Reports}, month = {11}, number = 1, pages = 20490, title = {Physics inspired compact modelling of BiFe₃ based memristors}, url = {https://doi.org/10.1038/s41598-022-24439-4}, volume = 12, year = 2022 }
  Link
  https://doi.org/10.1038/s41598-022-24439-4
6. Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. Hussam Amrouch; Krishnendu Chakrabarty; Dirk Pflüger; Ilia Polian; Matthias Sauer and Matteo Sonza Reorda. In 2022 IEEE European Test Symposium (ETS), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ETS54262.2022.9810416
  - BibTeX
  BibTeX
  @inproceedings{9810416, abteilung = {star hocos}, author = {Amrouch, Hussam and Chakrabarty, Krishnendu and Pflüger, Dirk and Polian, Ilia and Sauer, Matthias and Reorda, Matteo Sonza}, booktitle = {2022 IEEE European Test Symposium (ETS)}, doi = {10.1109/ETS54262.2022.9810416}, pages = {1-6}, title = {Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization}, year = 2022 }
7. Stochastic Computing Architectures for Lightweight LSTM Neural Networks. Roshwin Sengupta; Ilia Polian and John P. Hayes. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2022, pp. 124–129. DOI: https://doi.org/10.1109/DDECS54261.2022.9770167
  - BibTeX
  BibTeX
  @inproceedings{9770167, abteilung = {hocos}, author = {Sengupta, Roshwin and Polian, Ilia and Hayes, John P.}, booktitle = {2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)}, doi = {10.1109/DDECS54261.2022.9770167}, pages = {124-129}, title = {Stochastic Computing Architectures for Lightweight LSTM Neural Networks}, year = 2022 }
8. Benchmarking the performance of portfolio optimization with QAOA. Daniel Brandhofer, Sebastianand Braun; Vanessa Dehn; Gerhard Hellstern; Matthias Hüls; Yanjun Ji; Ilia Polian; Amandeep Singh Bhatia and Thomas Wellens. Quantum Information Processing 22, 1 (December 2022), pp. 25. DOI: https://doi.org/10.1007/s11128-022-03766-5
  Zusammenfassung
  We present a detailed study of portfolio optimization using different versions of the quantum approximate optimization algorithm (QAOA). For a given list of assets, the portfolio optimization problem is formulated as quadratic binary optimization constrained on the number of assets contained in the portfolio. QAOA has been suggested as a possible candidate for solving this problem (and similar combinatorial optimization problems) more efficiently than classical computers in the case of a sufficiently large number of assets. However, the practical implementation of this algorithm requires a careful consideration of several technical issues, not all of which are discussed in the present literature. The present article intends to fill this gap and thereby provides the reader with a useful guide for applying QAOA to the portfolio optimization problem (and similar problems). In particular, we will discuss several possible choices of the variational form and of different classical algorithms for finding the corresponding optimized parameters. Viewing at the application of QAOA on error-prone NISQ hardware, we also analyse the influence of statistical sampling errors (due to a finite number of shots) and gate and readout errors (due to imperfect quantum hardware). Finally, we define a criterion for distinguishing between `easy' and `hard' instances of the portfolio optimization problem.
  BibTeX
  @article{Brandhofer2022, abstract = {We present a detailed study of portfolio optimization using different versions of the quantum approximate optimization algorithm (QAOA). For a given list of assets, the portfolio optimization problem is formulated as quadratic binary optimization constrained on the number of assets contained in the portfolio. QAOA has been suggested as a possible candidate for solving this problem (and similar combinatorial optimization problems) more efficiently than classical computers in the case of a sufficiently large number of assets. However, the practical implementation of this algorithm requires a careful consideration of several technical issues, not all of which are discussed in the present literature. The present article intends to fill this gap and thereby provides the reader with a useful guide for applying QAOA to the portfolio optimization problem (and similar problems). In particular, we will discuss several possible choices of the variational form and of different classical algorithms for finding the corresponding optimized parameters. Viewing at the application of QAOA on error-prone NISQ hardware, we also analyse the influence of statistical sampling errors (due to a finite number of shots) and gate and readout errors (due to imperfect quantum hardware). Finally, we define a criterion for distinguishing between `easy' and `hard' instances of the portfolio optimization problem.}, abteilung = {hocos}, author = {{Brandhofer, Sebastianand Braun}, Daniel and Dehn, Vanessa and Hellstern, Gerhard and Hüls, Matthias and Ji, Yanjun and Polian, Ilia and Bhatia, Amandeep Singh and Wellens, Thomas}, day = 16, doi = {10.1007/s11128-022-03766-5}, issn = {1573-1332}, journal = {Quantum Information Processing}, month = {12}, number = 1, pages = 25, title = {Benchmarking the performance of portfolio optimization with QAOA}, url = {https://doi.org/10.1007/s11128-022-03766-5}, volume = 22, year = 2022 }
  Link
  https://doi.org/10.1007/s11128-022-03766-5
9. Security in an Approximated World: New Threats and Opportunities in the Approximate Computing Paradigm. Paolo Palmieri; Ilia Polian and Francesco Regazzoni. In Approximate Computing Techniques: From Component- to Application-Level, Alberto Bosio; Daniel Ménard and Olivier Sentieys (eds.). Springer International Publishing, Cham, 2022, pp. 323--348. DOI: https://doi.org/10.1007/978-3-030-94705-7_11
  Zusammenfassung
  As cyber-attacks grow in frequency and complexity every year, digital systems critically rely on complex security mechanisms. With Approximate Computing (AxC) reaching maturity for practical application, the long-neglected security implications of this paradigm must be understood and addressed. This chapter provides an overview of both: security threats potentially stemming from AxC hardware blocks, and opportunities for better security constructions based on AxC. Concerning the threats, we will discuss security issues related with design and manufacturing (reverse engineering, hardware Trojans, counterfeiting, and piracy) of approximate circuits and with their operation (side channel, covert-channel, and fault-injection attacks). For each threat, we will discuss the consequences of the transition from classical to approximate circuits. We will then present two promising applications of AxC technology in homomorphic encryption and in defending neural networks against adversarial attacks. Approximated homomorphic encryption can reduce the computational overhead of large-scale computations performed in the encrypted domain. We will provide an implementation angle for scenarios such as cloud computing or machine learning/AI, where the improved efficiency of the computation is particularly beneficial. Then, we will discuss how stochastic computing (a type of AxC) implementations of neural networks can be made more resilient against adversarial attacks while virtually retaining their classification accuracy.
  BibTeX
  @inbook{Palmieri2022, abstract = {As cyber-attacks grow in frequency and complexity every year, digital systems critically rely on complex security mechanisms. With Approximate Computing (AxC) reaching maturity for practical application, the long-neglected security implications of this paradigm must be understood and addressed. This chapter provides an overview of both: security threats potentially stemming from AxC hardware blocks, and opportunities for better security constructions based on AxC. Concerning the threats, we will discuss security issues related with design and manufacturing (reverse engineering, hardware Trojans, counterfeiting, and piracy) of approximate circuits and with their operation (side channel, covert-channel, and fault-injection attacks). For each threat, we will discuss the consequences of the transition from classical to approximate circuits. We will then present two promising applications of AxC technology in homomorphic encryption and in defending neural networks against adversarial attacks. Approximated homomorphic encryption can reduce the computational overhead of large-scale computations performed in the encrypted domain. We will provide an implementation angle for scenarios such as cloud computing or machine learning/AI, where the improved efficiency of the computation is particularly beneficial. Then, we will discuss how stochastic computing (a type of AxC) implementations of neural networks can be made more resilient against adversarial attacks while virtually retaining their classification accuracy.}, abteilung = {hocos}, address = {Cham}, author = {Palmieri, Paolo and Polian, Ilia and Regazzoni, Francesco}, booktitle = {Approximate Computing Techniques: From Component- to Application-Level}, doi = {10.1007/978-3-030-94705-7_11}, editor = {Bosio, Alberto and M{\'e}nard, Daniel and Sentieys, Olivier}, isbn = {978-3-030-94705-7}, pages = {323--348}, publisher = {Springer International Publishing}, title = {Security in an Approximated World: New Threats and Opportunities in the Approximate Computing Paradigm}, url = {https://doi.org/10.1007/978-3-030-94705-7_11}, year = 2022 }
  Link
  https://doi.org/10.1007/978-3-030-94705-7_11
10. On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks. Florian Neugebauer; Stefan Holst and Ilia Polian. In 2022 IEEE European Test Symposium (ETS), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ETS54262.2022.9810429
  - BibTeX
  BibTeX
  @inproceedings{9810429, abteilung = {hocos}, author = {Neugebauer, Florian and Holst, Stefan and Polian, Ilia}, booktitle = {2022 IEEE European Test Symposium (ETS)}, doi = {10.1109/ETS54262.2022.9810429}, pages = {1-6}, title = {On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks}, year = 2022 }
11. Second Harmonic Generation Exploiting Ultra-Stable Resistive Switching Devices for Secure Hardware Systems. Ziang Chen; Nan Du; Mahdi Kiani; Xianyue Zhao; Ilona Skorupa; Stefan E. Schulz; Danilo Bürger; Massimiliano Di Ventra; Ilia Polian and Heidemarie Schmidt. IEEE Transactions on Nanotechnology 21, (2022), pp. 71–80. DOI: https://doi.org/10.1109/TNANO.2021.3135713
  - BibTeX
  BibTeX
  @article{9652069, abteilung = {hocos}, author = {Chen, Ziang and Du, Nan and Kiani, Mahdi and Zhao, Xianyue and Skorupa, Ilona and Schulz, Stefan E. and Bürger, Danilo and Ventra, Massimiliano Di and Polian, Ilia and Schmidt, Heidemarie}, doi = {10.1109/TNANO.2021.3135713}, journal = {IEEE Transactions on Nanotechnology}, pages = {71-80}, title = {Second Harmonic Generation Exploiting Ultra-Stable Resistive Switching Devices for Secure Hardware Systems}, volume = 21, year = 2022 }
2021
1. ArsoNISQ: Analyzing Quantum Algorithms on Near-Term Architectures. Sebastian Brandhofer; Simon Devitt and Ilia Polian. In Proceedings of the 26th IEEE European Test Symposium (ETS’21), Virtual, 2021, pp. 1--6.
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  While scalable, fully error corrected quantum computing is years or even decades away, there is considerable interest in noisy intermediate-scale quantum computing (NISQ). In this paper, we introduce the ArsoNISQ framework that determines the tolerable error rate of a given quantum algorithm computation, i.e. quantum circuits, and the success probability of the computation given a success criterion and a NISQ computer. ArsoNISQ is based on simulations of quantum circuits subject to errors according to the Pauli error model. ArsoNISQ was evaluated on a set of quantum algorithms that can incur a quantum speedup or are otherwise relevant to NISQ computing. Despite optimistic expectations in recent literature, we did not observe quantum algorithms with intrinsic robustness, i.e. algorithms that tolerate one error on average, in this evaluation. The evaluation demonstrated, however, that the quantum circuit size sets an upper bound for its tolerable error rate and quantified the difference in tolerate error rates for quantum circuits of similar sizes. Thus, the framework can assist quantum algorithm developers in improving their implementation and selecting a suitable NISQ computing platform. Extrapolating the results into the quantum advantage regime suggests that the error rate of larger quantum computers must decrease substantially or active quantum error correction will need to be deployed for most of the evaluated algorithms
  BibTeX
  @inproceedings{BrandhSDIP2021, abstract = {While scalable, fully error corrected quantum computing is years or even decades away, there is considerable interest in noisy intermediate-scale quantum computing (NISQ). In this paper, we introduce the ArsoNISQ framework that determines the tolerable error rate of a given quantum algorithm computation, i.e. quantum circuits, and the success probability of the computation given a success criterion and a NISQ computer. ArsoNISQ is based on simulations of quantum circuits subject to errors according to the Pauli error model. ArsoNISQ was evaluated on a set of quantum algorithms that can incur a quantum speedup or are otherwise relevant to NISQ computing. Despite optimistic expectations in recent literature, we did not observe quantum algorithms with intrinsic robustness, i.e. algorithms that tolerate one error on average, in this evaluation. The evaluation demonstrated, however, that the quantum circuit size sets an upper bound for its tolerable error rate and quantified the difference in tolerate error rates for quantum circuits of similar sizes. Thus, the framework can assist quantum algorithm developers in improving their implementation and selecting a suitable NISQ computing platform. Extrapolating the results into the quantum advantage regime suggests that the error rate of larger quantum computers must decrease substantially or active quantum error correction will need to be deployed for most of the evaluated algorithms}, abteilung = {hocos}, author = {Brandhofer, Sebastian and Devitt, Simon and Polian, Ilia}, booktitle = {Proceedings of the 26th IEEE European Test Symposium (ETS'21)}, day = {24--28}, isbn = {978-1- 6654-1849-2}, location = {Virtual}, month = {05}, owner = {brandhsn}, pages = {1--6}, title = {ArsoNISQ: Analyzing Quantum Algorithms on Near-Term Architectures}, year = 2021 }
2. Towards Utilizing Self-awareness During System-level Test. Denis Schwachhofer; Steffen Becker; Matthias Sauer; Stefan Wagner and Ilia Polian. In 33. GI / GMM / ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ’21)), 2021.
  - BibTeX
  BibTeX
  @inproceedings{schwachhofer2021towards, abeilung = {hocos}, author = {Schwachhofer, Denis and Becker, Steffen and Sauer, Matthias and Wagner, Stefan and Polian, Ilia}, booktitle = {33. GI / GMM / ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ'21))}, day = {22--23}, month = {02}, title = {Towards Utilizing Self-awareness During System-level Test}, year = 2021 }
3. Noisy Intermediate-Scale Quantum (NISQ) Computers: How They Work, How They Fail, How to Test Them? Sebastian Brandhofer; Simon Devitt; Thomas Wellens and Ilia Polian. In Proceedings of the 39th IEEE VLSI Test Symposium (VTS’21), Virtual, 2021, pp. 1--6.
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  First quantum computers very recently have demonstrated “quantum supremacy” or “quantum advantage”: Executing a computation that would have been impossible on a classical machine. Today’s quantum computers follow the NISQ paradigm: They exhibit error rates that are much higher than in conventional electronics and have insufficient quantum resources to support powerful error correction protocols. This raises questions which relevant computations are within the reach of NISQ architectures. Several “NISQ-era algorithms” are assumed to match the specifics of such computers; for instance, variational optimisers are based on intertwining relatively short quantum and classical computations, thus maximizing the chances of success. This paper will critically assess the promise and challenge of NISQ computing. What has this field achieved so far, what are we likely to achieve soon, where do we have to be skeptical and wait for the advent of larger-scale fully error-corrected architectures?
  BibTeX
  @inproceedings{BrandhSDTWIP2021, abstract = {First quantum computers very recently have demonstrated “quantum supremacy” or “quantum advantage”: Executing a computation that would have been impossible on a classical machine. Today’s quantum computers follow the NISQ paradigm: They exhibit error rates that are much higher than in conventional electronics and have insufficient quantum resources to support powerful error correction protocols. This raises questions which relevant computations are within the reach of NISQ architectures. Several “NISQ-era algorithms” are assumed to match the specifics of such computers; for instance, variational optimisers are based on intertwining relatively short quantum and classical computations, thus maximizing the chances of success. This paper will critically assess the promise and challenge of NISQ computing. What has this field achieved so far, what are we likely to achieve soon, where do we have to be skeptical and wait for the advent of larger-scale fully error-corrected architectures?}, abteilung = {hocos}, author = {Brandhofer, Sebastian and Devitt, Simon and Wellens, Thomas and Polian, Ilia}, booktitle = {Proceedings of the 39th IEEE VLSI Test Symposium (VTS'21)}, day = {26--28}, isbn = {978-1-6654-1949-9}, location = {Virtual}, month = {04}, owner = {brandhsn}, pages = {1--6}, title = {Noisy Intermediate-Scale Quantum ({NISQ}) Computers: How They Work, How They Fail, How to Test Them?}, year = 2021 }
4. Machine Learning for Semiconductor Test and Reliability. Hussam Amrouch; Animesh Basak Chowdhury; Wentian Jin; Ramesh Karri; Khorrami Farshad; Prashanth Krishnamurthy; Ilia Polian; Victor M. van Santen; Benjamin Tan and Sheldon Tan. In IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.
  - BibTeX
  BibTeX
  @inproceedings{VTS21_SS, abteilung = {star hocos}, author = {Amrouch, Hussam and Chowdhury, Animesh Basak and Jin, Wentian and Karri, Ramesh and Farshad, Khorrami and Krishnamurthy, Prashanth and Polian, Ilia and M. van Santen, Victor and Tan, Benjamin and Tan, Sheldon}, booktitle = {IEEE VLSI Test Symposium (VTS'21)}, isbn = {978-1-6654-1949-9}, location = {Virtual}, month = {02}, title = {Machine Learning for Semiconductor Test and Reliability}, year = 2021 }
5. System-Level Test: State of the art and challenges. Davide Appello; H. H. Chen; Matthias Sauer; Ilia Polian; Paolo Bernardi and Matteo Sonza Reorda. In Proc. IEEE Int’l On-Line Test Test Symp., online, 2021.
  - BibTeX
  BibTeX
  @inproceedings{Appello2021system, abteilung = {hocos}, author = {Appello, Davide and Chen, H. H. and Sauer, Matthias and Polian, Ilia and Bernardi, Paolo and Sonza Reorda, Matteo}, booktitle = {Proc. IEEE Int'l On-Line Test Test Symp.}, location = {online}, title = {System-Level Test: State of the art and challenges}, year = 2021 }
6. Towards reliable in-memory computing: From emerging devices to post-von-Neumann architectures. Hussam Amrouch; Nan Du; Anteneh Gebregiorgis; Said Hamdioui and Ilia Polian. In Proc. IFIP / IEEE Int’l Conf. on Very Large Scale Integration (VLSI-SoC). (Accepted), online, 2021.
  - BibTeX
  BibTeX
  @inproceedings{Amrouch2021towards, abteilung = {star hocos}, author = {Amrouch, Hussam and Du, Nan and Gebregiorgis, Anteneh and Hamdioui, Said and Polian, Ilia}, booktitle = {Proc. IFIP / IEEE Int'l Conf. on Very Large Scale Integration (VLSI-SoC). (Accepted)}, location = {online}, title = {Towards reliable in-memory computing: From emerging devices to post-von-Neumann architectures}, year = 2021 }
7. Detection of malicious spatial-domain steganography over noisy channels. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. In Multidisciplinary Approach to Modern Digital Steganography, Sabyasachi Pramanik; Mangesh Manikrao Ghonge; Renjith V. Ravi and Korhan Cengiz (eds.). IGI Global, 2021.
  - BibTeX
  BibTeX
  @inbook{Prasad2021detection, abteilung = {hocos}, author = {Prasad, Swaroop Shankar and Hadar, Ofer and Polian, Ilia}, booktitle = {Multidisciplinary Approach to Modern Digital Steganography}, editor = {Pramanik, Sabyasachi and Manikrao Ghonge, Mangesh and Ravi, Renjith V. and Cengiz, Korhan}, isbn = {978-1-7998-7160-6}, publisher = {IGI Global}, title = {Detection of malicious spatial-domain steganography over noisy channels}, year = 2021 }
8. Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications. Ilia Polian; John P. Hayes; Vincent T. Lee and Weikang Qian. IEEE Design & Test 38, 6 (2021), pp. 5–15. DOI: https://doi.org/10.1109/MDAT.2021.3080989
  - BibTeX
  BibTeX
  @article{9639029, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P. and Lee, Vincent T. and Qian, Weikang}, doi = {10.1109/MDAT.2021.3080989}, journal = {IEEE Design & Test}, number = 6, pages = {5-15}, title = {Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications}, volume = 38, year = 2021 }
9. Extending circuit design flow for early assessment of fault attack vulnerabilities. Felipe Valencia; Ilia Polian and Francesco Regazzoni. In Proc. Euromicro Conf. on Digital System Design. (Accepted), online, 2021.
  - BibTeX
  BibTeX
  @inproceedings{Valencia2021extending, abteilung = {hocos}, author = {Valencia, Felipe and Polian, Ilia and Regazzoni, Francesco}, booktitle = {Proc. Euromicro Conf. on Digital System Design. (Accepted)}, location = {online}, title = {Extending circuit design flow for early assessment of fault attack vulnerabilities}, year = 2021 }
10. Protecting artificial intelligence IPs: a survey of watermarking and fingerprinting for machine learning. Francesco Regazzoni; Paolo Palmieri; Fethulah Smailbegovic; Rosario Cammarota and Ilia Polian. CAAI Transactions on Intelligence Technology 6, 2 (2021), pp. 180–191. DOI: https://doi.org/10.1049/cit2.12029
  Zusammenfassung
  Artificial intelligence (AI) algorithms achieve outstanding results in many application domains such as computer vision and natural language processing. The performance of AI models is the outcome of complex and costly model architecture design and training processes. Hence, it is paramount for model owners to protect their AI models from piracy – model cloning, illegitimate distribution and use. IP protection mechanisms have been applied to AI models, and in particular to deep neural networks, to verify the model ownership. State-of-the-art AI model ownership protection techniques have been surveyed. The pros and cons of AI model ownership protection have been reported. The majority of previous works are focused on watermarking, while more advanced methods such fingerprinting and attestation are promising but not yet explored in depth. This study has been concluded by discussing possible research directions in the area.
  BibTeX
  @article{Regazzoni2021artificial, abstract = {Artificial intelligence (AI) algorithms achieve outstanding results in many application domains such as computer vision and natural language processing. The performance of AI models is the outcome of complex and costly model architecture design and training processes. Hence, it is paramount for model owners to protect their AI models from piracy – model cloning, illegitimate distribution and use. IP protection mechanisms have been applied to AI models, and in particular to deep neural networks, to verify the model ownership. State-of-the-art AI model ownership protection techniques have been surveyed. The pros and cons of AI model ownership protection have been reported. The majority of previous works are focused on watermarking, while more advanced methods such fingerprinting and attestation are promising but not yet explored in depth. This study has been concluded by discussing possible research directions in the area.}, abteilung = {hocos}, author = {Regazzoni, Francesco and Palmieri, Paolo and Smailbegovic, Fethulah and Cammarota, Rosario and Polian, Ilia}, doi = {10.1049/cit2.12029}, issn = {2468-2322}, journal = {CAAI Transactions on Intelligence Technology}, number = 2, pages = {180-191}, title = {Protecting artificial intelligence IPs: a survey of watermarking and fingerprinting for machine learning}, url = {https://doi.org/10.1049/cit2.12029}, volume = 6, year = 2021 }
  Link
  https://doi.org/10.1049/cit2.12029
11. Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security. Domenic Forte; Debdeep Mukhopadhyay; Ilia Polian; Yunsi Fei and Rosario Cammarota. J. Emerg. Technol. Comput. Syst. 17, 3 (June 2021). DOI: https://doi.org/10.1145/3464326
  - BibTeX
  - Link
  BibTeX
  @article{10.1145/3464326, abteilung = {hocos}, address = {New York, NY, USA}, articleno = {29}, author = {Forte, Domenic and Mukhopadhyay, Debdeep and Polian, Ilia and Fei, Yunsi and Cammarota, Rosario}, doi = {10.1145/3464326}, issn = {1550-4832}, issue_date = {July 2021}, journal = {J. Emerg. Technol. Comput. Syst.}, month = {06}, number = 3, numpages = {4}, publisher = {Association for Computing Machinery}, title = {Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security}, url = {https://doi.org/10.1145/3464326}, volume = 17, year = 2021 }
  Link
  https://doi.org/10.1145/3464326
12. Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms. Sebastian Brandhofer; Ilia Polian and Hans Peter Büchler. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, pp. 1–7. DOI: https://doi.org/10.1109/ICCAD51958.2021.9643490
  - BibTeX
  BibTeX
  @inproceedings{9643490, abteilung = {hocos}, author = {Brandhofer, Sebastian and Polian, Ilia and Büchler, Hans Peter}, booktitle = {2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, doi = {10.1109/ICCAD51958.2021.9643490}, pages = {1-7}, title = {Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms}, year = 2021 }
13. Nano Security: From Nano-Electronics to Secure Systems. Ilia Polian; Frank Altmann; Tolga Arul; Christian Boit; Ralf Brederlow; Lucas Davi; Rolf Drechsler; Nan Du; Thomas Eisenbarth; Tim Güneysu; Sascha Hermann; Matthias Hiller; Rainer Leupers; Farhad Merchant; Thomas Mussenbrock; Stefan Katzenbeisser; Akash Kumar; Wolfgang Kunz; Thomas Mikolajick; Vivek Pachauri; Jean-Pierre Seifert; Frank Sill Torres and Jens Trommer. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’21), Virtual Event, 2021.
  - BibTeX
  BibTeX
  @inproceedings{polian2021security, abteilung = {hocos}, author = {Polian, Ilia and Altmann, Frank and Arul, Tolga and Boit, Christian and Brederlow, Ralf and Davi, Lucas and Drechsler, Rolf and Du, Nan and Eisenbarth, Thomas and Güneysu, Tim and Hermann, Sascha and Hiller, Matthias and Leupers, Rainer and Merchant, Farhad and Mussenbrock, Thomas and Katzenbeisser, Stefan and Kumar, Akash and Kunz, Wolfgang and Mikolajick, Thomas and Pachauri, Vivek and Seifert, Jean-Pierre and Torres, Frank Sill and Trommer, Jens}, booktitle = {Proceedings of the Conference on Design, Automation \& Test in Europe (\textbf{DATE'21})}, location = {Virtual Event}, month = {02}, title = {Nano Security: From Nano-Electronics to Secure Systems}, year = 2021 }
14. Security, Reliability and Test Aspects of the RISC-V Ecosystem. Jaume Abella; Sergi Alcaide; Jens Anders; Francisco Bas; Steffen Becker; Elke De Mulder; Nourhan Elhamawy; Frank K. Gürkaynak; Helena Handschuh; Carles Hernandez; Mike Hutter; Leonidas Kosmidis; Ilia Polian; Matthias Sauer; Stefan Wagner and Francesco Regazzoni. In Proceedings of the 26th IEEE European Test Symposium (ETS’21), 2021.
  - BibTeX
  BibTeX
  @inproceedings{abella2021security, abteilung = {hocos}, author = {Abella, Jaume and Alcaide, Sergi and Anders, Jens and Bas, Francisco and Becker, Steffen and De Mulder, Elke and Elhamawy, Nourhan and Gürkaynak, Frank K. and Handschuh, Helena and Hernandez, Carles and Hutter, Mike and Kosmidis, Leonidas and Polian, Ilia and Sauer, Matthias and Wagner, Stefan and Regazzoni, Francesco}, booktitle = {Proceedings of the 26th IEEE European Test Symposium (ETS'21)}, day = {24--28}, isbn = {978-1-6654-1849-2}, month = {05}, title = {Security, Reliability and Test Aspects of the RISC-V Ecosystem}, year = 2021 }
15. Low-power emerging memristive designs towards secure hardware systems for applications in internet of things. Nan Du; Heidemarie Schmidt and Ilia Polian. Nano Materials Science 3, 2 (2021), pp. 186–204.
  - BibTeX
  BibTeX
  @article{Du2021low, abteilung = {hocos}, author = {Du, Nan and Schmidt, Heidemarie and Polian, Ilia}, issn = {2589-9651}, journal = {Nano Materials Science}, number = 2, pages = {186-204}, project = {memcrypto}, title = {Low-power emerging memristive designs towards secure hardware systems for applications in internet of things}, volume = 3, year = 2021 }
16. Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities. Felipe Valencia; Ilia Polian and Francesco Regazzoni. In 2021 24th Euromicro Conference on Digital System Design (DSD), 2021, pp. 385–388. DOI: https://doi.org/10.1109/DSD53832.2021.00065
  - BibTeX
  BibTeX
  @inproceedings{9556359, abteilung = {hocos}, author = {Valencia, Felipe and Polian, Ilia and Regazzoni, Francesco}, booktitle = {2021 24th Euromicro Conference on Digital System Design (DSD)}, doi = {10.1109/DSD53832.2021.00065}, pages = {385-388}, title = {Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities}, year = 2021 }
17. Error Analysis of the Variational Quantum Eigensolver Algorithm. Sebastian Brandhofer; Simon Devitt and Ilia Polian. In 2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2021, pp. 1–6. DOI: https://doi.org/10.1109/NANOARCH53687.2021.9642249
  - BibTeX
  BibTeX
  @inproceedings{VQE_ERROR, abteilung = {hocos}, author = {Brandhofer, Sebastian and Devitt, Simon and Polian, Ilia}, booktitle = {2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)}, doi = {10.1109/NANOARCH53687.2021.9642249}, pages = {1-6}, title = {Error Analysis of the Variational Quantum Eigensolver Algorithm}, year = 2021 }
2020
1. IPM-RED: combining higher-order masking with robust error detection. Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (June 2020). DOI: https://doi.org/10.1007/s13389-020-00229-4
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  Cryptographic hardware becomes increasingly vulnerable to physical attacks--both passive side-channel analysis and active fault injections--performed by skillful and well-equipped adversaries. In this paper, we introduce a technique that provides very high security against both types of attacks. It combines inner product masking (IPM), which offers higher-order side-channel attack resistance on word level and on bit level, with nonlinear security-oriented error-detection codes that provide robustness, i.e., strong detection guarantees for arbitrary faults. We prove that our scheme has the same security against side-channel attacks that an earlier, non-robust IPM-based solution has and in addition preserves robustness during addition and multiplication (and therefore arbitrary computations). Moreover, we prove that the information leakage from the checker is small and that the attack will be detected far before the attacker will gain significant information.
  BibTeX
  @article{keren2020ipmred, abstract = {Cryptographic hardware becomes increasingly vulnerable to physical attacks--both passive side-channel analysis and active fault injections--performed by skillful and well-equipped adversaries. In this paper, we introduce a technique that provides very high security against both types of attacks. It combines inner product masking (IPM), which offers higher-order side-channel attack resistance on word level and on bit level, with nonlinear security-oriented error-detection codes that provide robustness, i.e., strong detection guarantees for arbitrary faults. We prove that our scheme has the same security against side-channel attacks that an earlier, non-robust IPM-based solution has and in addition preserves robustness during addition and multiplication (and therefore arbitrary computations). Moreover, we prove that the information leakage from the checker is small and that the attack will be detected far before the attacker will gain significant information.}, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia}, doi = {10.1007/s13389-020-00229-4}, issn = {2190-8516}, journal = {Journal of Cryptographic Engineering}, month = {06}, title = {IPM-RED: combining higher-order masking with robust error detection.}, volume = 10, year = 2020 }
2. Information leakage from robust codes protecting cryptographic primitives. Osnat Keren and Ilia Polian. In Frontiers in Hardware Security and Trust: Theory, design and practice, C.H. Chang and Y Cao (eds.). The Institution of Engineering and Technology, 2020.
  - BibTeX
  BibTeX
  @inbook{keren2020information, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia}, booktitle = {Frontiers in Hardware Security and Trust: Theory, design and practice}, editor = {Chang, C.H. and Cao, Y}, isbn = {978-1-78561-927-4}, publisher = {The Institution of Engineering and Technology}, title = {Information leakage from robust codes protecting cryptographic primitives}, year = 2020 }
3. Error control scheme for malicious and natural faults in cryptographic modules. Mael Gay; Batya Karp; Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (June 2020). DOI: https://doi.org/10.1007/s13389-020-00234-7
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  Today’s electronic systems must simultaneously fulfill strict requirements on security and reliability. In particular, their cryptographic modules are exposed to faults, which can be due to natural failures (e.g., radiation or electromagnetic noise) or malicious fault-injection attacks. We present an architecture based on a new class of error-detecting codes that combine robustness properties with a minimal distance. The new architecture guarantees (with some probability) the detection of faults injected by an intelligent and strategic adversary who can precisely control the disturbance. At the same time it supports automatic correction of low-multiplicity faults. To this end, we discuss an efficient technique to correct single nibble/byte errors while avoiding full syndrome analysis. We also examine a Compact Protection Code (CPC)-based system level fault manager that considers this code an inner code (and the CPC as its outer code). We report experimental results obtained by physical fault injection on the SAKURA-G FPGA board. The experimental results reconfirm the assumption that faults may cause an arbitrary number of bit flips. They indicate that a combined inner–outer coding scheme can significantly reduce the number of fault events that go undetected due to erroneous corrections of the inner code.
  BibTeX
  @article{gay2020error, abstract = {Today’s electronic systems must simultaneously fulfill strict requirements on security and reliability. In particular, their cryptographic modules are exposed to faults, which can be due to natural failures (e.g., radiation or electromagnetic noise) or malicious fault-injection attacks. We present an architecture based on a new class of error-detecting codes that combine robustness properties with a minimal distance. The new architecture guarantees (with some probability) the detection of faults injected by an intelligent and strategic adversary who can precisely control the disturbance. At the same time it supports automatic correction of low-multiplicity faults. To this end, we discuss an efficient technique to correct single nibble/byte errors while avoiding full syndrome analysis. We also examine a Compact Protection Code (CPC)-based system level fault manager that considers this code an inner code (and the CPC as its outer code). We report experimental results obtained by physical fault injection on the SAKURA-G FPGA board. The experimental results reconfirm the assumption that faults may cause an arbitrary number of bit flips. They indicate that a combined inner–outer coding scheme can significantly reduce the number of fault events that go undetected due to erroneous corrections of the inner code.}, abteilung = {hocos}, author = {Gay, Mael and Karp, Batya and Keren, Osnat and Polian, Ilia}, doi = {10.1007/s13389-020-00234-7}, issn = {2190-8516}, journal = {Journal of Cryptographic Engineering}, month = {06}, title = {Error control scheme for malicious and natural faults in cryptographic modules}, volume = 10, year = 2020 }
4. Side Channel Attacks vs Approximated Computing. Francesco Regazzoni and Ilia Polian. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI 2020 (GLSVLSI ’20), 2020, pp. 321–326. DOI: https://doi.org/10.1145/3386263.3407592
  - BibTeX
  BibTeX
  @inproceedings{regazzoni2020channel, abteilung = {hocos}, author = {Regazzoni, Francesco and Polian, Ilia}, booktitle = {Proceedings of the 30th ACM Great Lakes Symposium on VLSI 2020 (GLSVLSI '20)}, doi = {10.1145/3386263.3407592}, isbn = {978-1-4503-7944-1}, month = {09}, pages = {321-326}, title = {Side Channel Attacks vs Approximated Computing}, year = 2020 }
5. An Open-Source Area-Optimized ECEG Cryptosystem in Hardware. Nourhan Elhamawy; Mael Gay and Ilia Polian. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 120–125. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00031
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  Hardware implementations of advanced cryptographic schemes gain importance for emerging cyber-physical and autonomous systems and with that the need for area-optimized hardware is also increasing. In this paper, we present a scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block. With the help of the Universal Elliptic Curve Arithmetic unit, that is designed to perform elliptic curve point multiplication, doubling and addition, the area has been kept to a minimum to fit on the Xilinx Spartan-6 LX75 FPGA. The design supports the NIST-recommended curves over prime fields.
  BibTeX
  @inproceedings{9154961, abstract = {Hardware implementations of advanced cryptographic schemes gain importance for emerging cyber-physical and autonomous systems and with that the need for area-optimized hardware is also increasing. In this paper, we present a scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block. With the help of the Universal Elliptic Curve Arithmetic unit, that is designed to perform elliptic curve point multiplication, doubling and addition, the area has been kept to a minimum to fit on the Xilinx Spartan-6 LX75 FPGA. The design supports the NIST-recommended curves over prime fields.}, abteilung = {hocos}, author = {Elhamawy, Nourhan and Gay, Mael and Polian, Ilia}, booktitle = {2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, doi = {10.1109/ISVLSI49217.2020.00031}, isbn = {978-1-7281-5775-7}, issn = {2159-3477}, month = {07}, pages = {120-125}, title = {An Open-Source Area-Optimized ECEG Cryptosystem in Hardware}, year = 2020 }
6. Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. Junseok Oh; Florian Neugebauer; Ilia Polian and John Hayes. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 246–251. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00052
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  Stochastic computing (SC) is a promising computation technique for applications with huge numbers of individually simple operations. One of the main application targets for SC is the design of convolutional neural networks (CNNs) due to their heavy reliance on multiply-accumulate operations that have compact and power-efficient SC realizations. We present a training optimization method that can improve the accuracy of SC-based CNNs significantly. Using regularization techniques in combination with a newly developed retraining algorithm, we enforce sparsity, reduce the number of required MUX-based additions, and thus minimize undesired downscaling. Our results show that the proposed regularized training procedure (RTP) can reduce the computation time of SC-based NNs by a factor of four without sacrificing classification accuracy while also reducing area in hardware implementations. These findings suggest that SC can be successfully applied to more powerful CNNs than previously thought possible, thus extending the range of potential uses of SC.
  BibTeX
  @inproceedings{9154942, abstract = {Stochastic computing (SC) is a promising computation technique for applications with huge numbers of individually simple operations. One of the main application targets for SC is the design of convolutional neural networks (CNNs) due to their heavy reliance on multiply-accumulate operations that have compact and power-efficient SC realizations. We present a training optimization method that can improve the accuracy of SC-based CNNs significantly. Using regularization techniques in combination with a newly developed retraining algorithm, we enforce sparsity, reduce the number of required MUX-based additions, and thus minimize undesired downscaling. Our results show that the proposed regularized training procedure (RTP) can reduce the computation time of SC-based NNs by a factor of four without sacrificing classification accuracy while also reducing area in hardware implementations. These findings suggest that SC can be successfully applied to more powerful CNNs than previously thought possible, thus extending the range of potential uses of SC.}, abteilung = {hocos}, author = {{Oh}, Junseok and {Neugebauer}, Florian and {Polian}, Ilia and {Hayes}, John}, booktitle = {2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, doi = {10.1109/ISVLSI49217.2020.00052}, isbn = {978-1-7281-5775-7}, issn = {2159-3477}, month = {07}, pages = {246-251}, title = {Retraining and Regularization to Optimize Neural Networks for Stochastic Computing}, year = 2020 }
7. Machine learning and hardware security: challenges and opportunities. Francesco Regazzoni; Shivam Bhasin; Amir Ali Pour; Ihab Alshaer; Furkan Aydin; Aydin Aysu; Vincent Beroulle; Giorgio Di Natal; Paul Franzon; David Hely; Naofumi Homma; Akira Ito; Dirmanto Jap; Priyank Kashyap; Ilia Polian; Seetal Potluri; Rei Ueno; Elena Ioana Vatajelu and Ville Yli-Mayry. In Proceedings of the 39th IEEE International Conference On Computer Aided Design 2020 (ICCAD’20), 2020.
  - BibTeX
  BibTeX
  @inproceedings{regazzoni2020machine, abteilung = {hocos}, author = {Regazzoni, Francesco and Bhasin, Shivam and Ali Pour, Amir and Alshaer, Ihab and Aydin, Furkan and Aysu, Aydin and Beroulle, Vincent and Di Natal, Giorgio and Franzon, Paul and Hely, David and Homma, Naofumi and Ito, Akira and Jap, Dirmanto and Kashyap, Priyank and Polian, Ilia and Potluri, Seetal and Ueno, Rei and Vatajelu, Elena Ioana and Yli-Mayry, Ville}, booktitle = {Proceedings of the 39th IEEE International Conference On Computer Aided Design 2020 (ICCAD'20)}, isbn = {978-1-4503-8026-3}, month = {11}, title = {Machine learning and hardware security: challenges and opportunities}, year = 2020 }
8. Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. Junseok Oh; Florian Neugebauer; Ilia Polian and John Hayes. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 246–251. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00052
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  Stochastic computing (SC) is a promising computation technique for applications with huge numbers of individually simple operations. One of the main application targets for SC is the design of convolutional neural networks (CNNs) due to their heavy reliance on multiply-accumulate operations that have compact and power-efficient SC realizations. We present a training optimization method that can improve the accuracy of SC-based CNNs significantly. Using regularization techniques in combination with a newly developed retraining algorithm, we enforce sparsity, reduce the number of required MUX-based additions, and thus minimize undesired downscaling. Our results show that the proposed regularized training procedure (RTP) can reduce the computation time of SC-based NNs by a factor of four without sacrificing classification accuracy while also reducing area in hardware implementations. These findings suggest that SC can be successfully applied to more powerful CNNs than previously thought possible, thus extending the range of potential uses of SC.
  BibTeX
  @inproceedings{9154942, abstract = {Stochastic computing (SC) is a promising computation technique for applications with huge numbers of individually simple operations. One of the main application targets for SC is the design of convolutional neural networks (CNNs) due to their heavy reliance on multiply-accumulate operations that have compact and power-efficient SC realizations. We present a training optimization method that can improve the accuracy of SC-based CNNs significantly. Using regularization techniques in combination with a newly developed retraining algorithm, we enforce sparsity, reduce the number of required MUX-based additions, and thus minimize undesired downscaling. Our results show that the proposed regularized training procedure (RTP) can reduce the computation time of SC-based NNs by a factor of four without sacrificing classification accuracy while also reducing area in hardware implementations. These findings suggest that SC can be successfully applied to more powerful CNNs than previously thought possible, thus extending the range of potential uses of SC.}, abteilung = {hocos}, author = {{Oh}, Junseok and {Neugebauer}, Florian and {Polian}, Ilia and {Hayes}, John}, booktitle = {2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, doi = {10.1109/ISVLSI49217.2020.00052}, isbn = {978-1-7281-5775-7}, issn = {2159-3477}, month = {07}, pages = {246-251}, title = {Retraining and Regularization to Optimize Neural Networks for Stochastic Computing}, year = 2020 }
9. Detection of malicious spatial-domain steganography over noisy channels using convolutional neural networks. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. In Proc. Media Watermarking, Security, and Forensics Conference at IS&T Electronic Imaging, 2020. DOI: https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
  Zusammenfassung
  Image steganography can have legitimate uses, for example, augmenting an image with a watermark for copyright reasons, but can also be utilized for malicious purposes. We investigate the detection of malicious steganography using neural networkbased classification when images are transmitted through a noisy channel. Noise makes detection harder because the classifier must not only detect perturbations in the image but also decide whether they are due to the malicious steganographic modifications or due to natural noise. Our results show that reliable detection is possible even for state-of-the-art steganographic algorithms that insert stego bits not affecting an image’s visual quality. The detection accuracy is high (above 85%) if the payload, or the amount of the steganographic content in an image, exceeds a certain threshold. At the same time, noise critically affects the steganographic information being transmitted, both through desynchronization (destruction of information which bits of the image contain steganographic information) and by flipping these bits themselves. This will force the adversary to use a redundant encoding with a substantial number of error-correction bits for reliable transmission, making detection feasible even for small payloads.
  BibTeX
  @inproceedings{Prasad2021detectionof, abstract = {Image steganography can have legitimate uses, for example, augmenting an image with a watermark for copyright reasons, but can also be utilized for malicious purposes. We investigate the detection of malicious steganography using neural networkbased classification when images are transmitted through a noisy channel. Noise makes detection harder because the classifier must not only detect perturbations in the image but also decide whether they are due to the malicious steganographic modifications or due to natural noise. Our results show that reliable detection is possible even for state-of-the-art steganographic algorithms that insert stego bits not affecting an image’s visual quality. The detection accuracy is high (above 85%) if the payload, or the amount of the steganographic content in an image, exceeds a certain threshold. At the same time, noise critically affects the steganographic information being transmitted, both through desynchronization (destruction of information which bits of the image contain steganographic information) and by flipping these bits themselves. This will force the adversary to use a redundant encoding with a substantial number of error-correction bits for reliable transmission, making detection feasible even for small payloads.}, abteilung = {hocos}, author = {Prasad, Swaroop Shankar and Hadar, Ofer and Polian, Ilia}, booktitle = {Proc. Media Watermarking, Security, and Forensics Conference at IS&T Electronic Imaging}, doi = {10.2352/ISSN.2470-1173.2020.4.MWSF-076}, issn = {2470-1173}, title = {Detection of malicious spatial-domain steganography over noisy channels using convolutional neural networks}, url = {https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076}, year = 2020 }
  Link
  https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
10. Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. Johann Knechtel; Elif Bilge Kavun; Francesco Regazzoni; Annelie Heuser; Anupam Chattopadhyay; Debdeep Mukhopadhyay; Soumyajit Dey; Yunsi Fei; Yaacov Belenky; Itamar Levi; Tim Güneysu; Patrick Schaumont and Ilia Polian. In 2020 Design, Automation Test in Europe Conference Exhibition (DATE), 2020, pp. 508–513. DOI: https://doi.org/10.23919/DATE48585.2020.9116483
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  Modern electronic systems become evermore complex, yet remain modular, with integrated circuits (ICs) acting as versatile hardware components at their heart. Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area. However, given the rise of hardware-centric security threats, we believe that EDA must also adopt related notions like secure by design and secure composition of hardware. Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative cross-effects.In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. We then discuss strategies and challenges for advancing research and development toward secure composition of circuits and systems.
  BibTeX
  @inproceedings{9116483, abstract = {Modern electronic systems become evermore complex, yet remain modular, with integrated circuits (ICs) acting as versatile hardware components at their heart. Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area. However, given the rise of hardware-centric security threats, we believe that EDA must also adopt related notions like secure by design and secure composition of hardware. Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative cross-effects.In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. We then discuss strategies and challenges for advancing research and development toward secure composition of circuits and systems.}, abteilung = {hocos}, author = {Knechtel, Johann and Kavun, Elif Bilge and Regazzoni, Francesco and Heuser, Annelie and Chattopadhyay, Anupam and Mukhopadhyay, Debdeep and Dey, Soumyajit and Fei, Yunsi and Belenky, Yaacov and Levi, Itamar and Güneysu, Tim and Schaumont, Patrick and Polian, Ilia}, booktitle = {2020 Design, Automation Test in Europe Conference Exhibition (DATE)}, doi = {10.23919/DATE48585.2020.9116483}, isbn = {978-3-9819263-4-7}, issn = {1558-1101}, month = {03}, pages = {508-513}, title = {Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA}, year = 2020 }
11. Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. Electronic Imaging 2020, 4 (January 2020), pp. 76-1-76–7. DOI: https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
  Zusammenfassung
  Image steganography can have legitimate uses, for example, augmenting an image with a watermark for copyright reasons, but can also be utilized for malicious purposes. We investigate the detection of malicious steganography using neural networkbased classification when images are transmitted through a noisy channel. Noise makes detection harder because the classifier must not only detect perturbations in the image but also decide whether they are due to the malicious steganographic modifications or due to natural noise. Our results show that reliable detection is possible even for state-of-the-art steganographic algorithms that insert stego bits not affecting an images visual quality. The detection accuracy is high (above 85%) if the payload, or the amount of the steganographic content in an image, exceeds a certain threshold. At the same time, noise critically affects the steganographic information being transmitted, both through desynchronization (destruction of information which bits of the image contain steganographic information) and by flipping these bits themselves. This will force the adversary to use a redundant encoding with a substantial number of error-correction bits for reliable transmission, making detection feasible even for small payloads.
  BibTeX
  @article{prasad2020detection, abstract = {Image steganography can have legitimate uses, for example, augmenting an image with a watermark for copyright reasons, but can also be utilized for malicious purposes. We investigate the detection of malicious steganography using neural networkbased classification when images are transmitted through a noisy channel. Noise makes detection harder because the classifier must not only detect perturbations in the image but also decide whether they are due to the malicious steganographic modifications or due to natural noise. Our results show that reliable detection is possible even for state-of-the-art steganographic algorithms that insert stego bits not affecting an images visual quality. The detection accuracy is high (above 85%) if the payload, or the amount of the steganographic content in an image, exceeds a certain threshold. At the same time, noise critically affects the steganographic information being transmitted, both through desynchronization (destruction of information which bits of the image contain steganographic information) and by flipping these bits themselves. This will force the adversary to use a redundant encoding with a substantial number of error-correction bits for reliable transmission, making detection feasible even for small payloads.}, abteilung = {hocos}, author = {Prasad, Swaroop Shankar and Hadar, Ofer and Polian, Ilia}, doi = {10.2352/ISSN.2470-1173.2020.4.MWSF-076}, issn = {2470-1173}, journal = {Electronic Imaging}, month = {01}, number = 4, pages = {76-1-76-7}, title = {Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks}, url = {https://www.ingentaconnect.com/content/ist/ei/2020/00002020/00000004/art00007}, volume = 2020, year = 2020 }
  Link
  https://www.ingentaconnect.com/content/ist/ei/2020/00002020/00000004/art00007
12. Hardware-based fast real-time image classification with stochastic computing. Ponana Kelettira Muthappa; Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 38th IEEE International Conference on Computer Design (ICCD’20), 2020.
  - BibTeX
  BibTeX
  @inproceedings{kelettiramuthappa2020hardwarebased, abteilung = {hocos}, author = {Kelettira Muthappa, Ponana and Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, booktitle = {Proceedings of the 38th IEEE International Conference on Computer Design (ICCD'20)}, isbn = {978-1-7281-9710-4}, month = {10}, title = {Hardware-based fast real-time image classification with stochastic computing}, year = 2020 }
13. Exploring the mysteries of system-level test. Ilia Polian; Jens Anders; Stefan Becker; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer; Adith Singh; Matteo Sonza Reorda and Stefan Wagner. In Proceedings of the 29th IEEE Asian Test Symposium (ATS’20), 2020.
  - BibTeX
  BibTeX
  @inproceedings{polian2020exploring, abteilung = {hocos}, author = {Polian, Ilia and Anders, Jens and Becker, Stefan and Bernardi, Paolo and Chakrabarty, Krishnendu and Elhamawy, Nourhan and Sauer, Matthias and Singh, Adith and Sonza Reorda, Matteo and Wagner, Stefan}, booktitle = {Proceedings of the 29th IEEE Asian Test Symposium (ATS'20)}, month = {11}, title = {Exploring the mysteries of system-level test.}, year = 2020 }
2019
1. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/cf/NeugebauerPH19, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 16th {ACM} International Conference on Computing Frontiers, {CF} 2019, Alghero, Italy, April 30 - May 2, 2019.}, crossref = {DBLP:conf/cf/2019}, doi = {10.1145/3310273.3323050}, pages = {59--66}, title = {On the maximum function in stochastic computing}, url = {https://doi.org/10.1145/3310273.3323050}, year = 2019 }
  Link
  https://doi.org/10.1145/3310273.3323050
2. On the Limits of Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In 2019 IEEE International Conference on Rebooting Computing, ICRC, 2019, pp. 98--105. DOI: https://doi.org/10.1109/ICRC.2019.8914706
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/icrc/NeugebauerPH19, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2019 {IEEE} International Conference on Rebooting Computing, {ICRC}}, day = {6--8}, doi = {10.1109/ICRC.2019.8914706}, month = {11}, pages = {98--105}, publisher = {{IEEE}}, title = {On the Limits of Stochastic Computing}, url = {https://doi.org/10.1109/ICRC.2019.8914706}, year = 2019 }
  Link
  https://doi.org/10.1109/ICRC.2019.8914706
3. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/cf/NeugebauerPH19, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 16th {ACM} International Conference on Computing Frontiers, {CF} 2019, Alghero, Italy, April 30 - May 2, 2019.}, crossref = {DBLP:conf/cf/2019}, doi = {10.1145/3310273.3323050}, pages = {59--66}, title = {On the maximum function in stochastic computing}, url = {https://doi.org/10.1145/3310273.3323050}, year = 2019 }
  Link
  https://doi.org/10.1145/3310273.3323050
4. Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support. Mael Gay; Tobias Paxian; Devanshi Upadhyaya; Bernd Becker and Ilia Polian. In 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2019, pp. 25–32. DOI: https://doi.org/10.1109/FDTC.2019.00012
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.
  BibTeX
  @inproceedings{8844472, abstract = {The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.}, abteilung = {hocos}, author = {Gay, Mael and Paxian, Tobias and Upadhyaya, Devanshi and Becker, Bernd and Polian, Ilia}, booktitle = {2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)}, doi = {10.1109/FDTC.2019.00012}, month = {08}, pages = {25-32}, title = {Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support}, year = 2019 }
5. A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives. Osnat Keren and Ilia Polian. In Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019, pp. 49--63. DOI: https://doi.org/10.29007/r2sc
  - BibTeX
  - Link
  BibTeX
  @inproceedings{PROOFS2019:comment_on_information_leakage, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia}, bibsource = {EasyChair, https://easychair.org}, booktitle = {Proceedings of 8th International Workshop on Security Proofs for Embedded Systems}, doi = {10.29007/r2sc}, editor = {Heydemann, Karine and K\textbackslash{}"uhne, Ulrich and Li, Letitia}, issn = {2515-1762}, pages = {49--63}, publisher = {EasyChair}, series = {Kalpa Publications in Computing}, title = {A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives}, url = {https://easychair.org/publications/paper/ZDvk}, volume = 11, year = 2019 }
  Link
  https://easychair.org/publications/paper/ZDvk
6. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian19, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1515/itit-2019-0008}, journal = {it - Information Technology}, number = 1, pages = {1--2}, title = {Hardware-oriented security}, url = {https://doi.org/10.1515/itit-2019-0008}, volume = 61, year = 2019 }
  Link
  https://doi.org/10.1515/itit-2019-0008
7. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
  Zusammenfassung
  Fault attacks are an essential threat to security of cryptographic functions. This chapter focuses on underlying concepts of fault attacks on cryptographic circuit implementations. Rather than targeting a specific cipher, the presented approach aims at an automatic construction of fault attacks from the circuit description. A Boolean formula that describes the circuit operation and the fault injection is generated and handed over to a SAT solver; an adversary can deduce protected information, e.g., the secret key, from the solution. The chapter also includes a comparison of the described methodology with other existing fault attack frameworks that are not specifically targeted towards circuit implementations.
  BibTeX
  @inbook{polian2019automatic, abstract = {Fault attacks are an essential threat to security of cryptographic functions. This chapter focuses on underlying concepts of fault attacks on cryptographic circuit implementations. Rather than targeting a specific cipher, the presented approach aims at an automatic construction of fault attacks from the circuit description. A Boolean formula that describes the circuit operation and the fault injection is generated and handed over to a SAT solver; an adversary can deduce protected information, e.g., the secret key, from the solution. The chapter also includes a comparison of the described methodology with other existing fault attack frameworks that are not specifically targeted towards circuit implementations.}, abteilung = {hocos}, address = {Cham}, author = {Polian, Ilia and Gay, Maël and Paxian, Tobias and Sauer, Matthias and Becker, Bernd}, booktitle = {Automated Methods in Cryptographic Fault Analysis}, chapter = 6, doi = {10.1007/978-3-030-11333-9_6}, editor = {Breier, Jakub and Hou, Xiaolu and Bhasin, Shivam}, isbn = {978-3-030-11332-2}, pages = {151-170}, publisher = {Springer International Publishing}, title = {Automatic construction of fault attacks on cryptographic hardware implementations}, url = {https://doi.org/10.1007/978-3-030-11333-9_6}, year = 2019 }
  Link
  https://doi.org/10.1007/978-3-030-11333-9_6
8. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
  Zusammenfassung
  Fault attacks are an essential threat to security of cryptographic functions. This chapter focuses on underlying concepts of fault attacks on cryptographic circuit implementations. Rather than targeting a specific cipher, the presented approach aims at an automatic construction of fault attacks from the circuit description. A Boolean formula that describes the circuit operation and the fault injection is generated and handed over to a SAT solver; an adversary can deduce protected information, e.g., the secret key, from the solution. The chapter also includes a comparison of the described methodology with other existing fault attack frameworks that are not specifically targeted towards circuit implementations.
  BibTeX
  @inbook{polian2019automatic, abstract = {Fault attacks are an essential threat to security of cryptographic functions. This chapter focuses on underlying concepts of fault attacks on cryptographic circuit implementations. Rather than targeting a specific cipher, the presented approach aims at an automatic construction of fault attacks from the circuit description. A Boolean formula that describes the circuit operation and the fault injection is generated and handed over to a SAT solver; an adversary can deduce protected information, e.g., the secret key, from the solution. The chapter also includes a comparison of the described methodology with other existing fault attack frameworks that are not specifically targeted towards circuit implementations.}, abteilung = {hocos}, address = {Cham}, author = {Polian, Ilia and Gay, Maël and Paxian, Tobias and Sauer, Matthias and Becker, Bernd}, booktitle = {Automated Methods in Cryptographic Fault Analysis}, chapter = 6, doi = {10.1007/978-3-030-11333-9_6}, editor = {Breier, Jakub and Hou, Xiaolu and Bhasin, Shivam}, isbn = {978-3-030-11332-2}, pages = {151-170}, publisher = {Springer International Publishing}, title = {Automatic construction of fault attacks on cryptographic hardware implementations}, url = {https://doi.org/10.1007/978-3-030-11333-9_6}, year = 2019 }
  Link
  https://doi.org/10.1007/978-3-030-11333-9_6
9. Improving Testability and Reliability of Advanced SRAM Architectures. Josef Kinseher; Moritz Völker and Ilia Polian. IEEE Trans. Emerging Topics Comput. 7, 3 (2019), pp. 456–467.
  - BibTeX
  - Link
  BibTeX
  @article{journals/tetc/KinseherVP19, author = {Kinseher, Josef and Völker, Moritz and Polian, Ilia}, ee = {https://doi.org/10.1109/TETC.2017.2677400}, issn = {2168-6750}, journal = {IEEE Trans. Emerging Topics Comput.}, number = 3, pages = {456-467}, title = {Improving Testability and Reliability of Advanced SRAM Architectures.}, url = {http://dblp.uni-trier.de/db/journals/tetc/tetc7.html#KinseherVP19}, volume = 7, year = 2019 }
  Link
  http://dblp.uni-trier.de/db/journals/tetc/tetc7.html#KinseherVP19
10. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian19, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1515/itit-2019-0008}, journal = {it - Information Technology}, number = 1, pages = {1--2}, title = {Hardware-oriented security}, url = {https://doi.org/10.1515/itit-2019-0008}, volume = 61, year = 2019 }
  Link
  https://doi.org/10.1515/itit-2019-0008
2018
1. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewme/PolianG18, abteilung = {hocos}, author = {Polian, Ilia and Gay, Mael}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {12th European Workshop on Microelectronics Education, {EWME} 2018, Braunschweig, Germany, September 24-26, 2018}, crossref = {DBLP:conf/ewme/2018}, doi = {10.1109/EWME.2018.8629483}, pages = {59--62}, title = {Hardware-oriented Security in a Computer Science Curriculum}, url = {https://doi.org/10.1109/EWME.2018.8629483}, year = 2018 }
  Link
  https://doi.org/10.1109/EWME.2018.8629483
2. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/esl/Polian18, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/LES.2017.2754446}, journal = {Embedded Systems Letters}, number = 1, pages = {26--29}, title = {Test and Reliability Challenges for Approximate Circuitry}, url = {https://doi.org/10.1109/LES.2017.2754446}, volume = 10, year = 2018 }
  Link
  https://doi.org/10.1109/LES.2017.2754446
3. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/mam/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1016/j.micpro.2018.06.009}, journal = {Microprocessors and Microsystems - Embedded Hardware Design}, pages = {316--326}, title = {S-box-based random number generation for stochastic computing}, url = {https://doi.org/10.1016/j.micpro.2018.06.009}, volume = 61, year = 2018 }
  Link
  https://doi.org/10.1016/j.micpro.2018.06.009
4. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/samos/RegazzoniFP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Fowler, Austin G. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018.}, crossref = {DBLP:conf/samos/2018}, doi = {10.1145/3229631.3264737}, pages = {173--178}, title = {Quantum era challenges for classical computers}, url = {https://doi.org/10.1145/3229631.3264737}, year = 2018 }
  Link
  https://doi.org/10.1145/3229631.3264737
5. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ches/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Ma{\"{e}}l and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{PROOFS} 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with {CHES} 2018, Amsterdam, The Netherlands, September 13, 2018}, crossref = {DBLP:conf/ches/2018proofs}, pages = {68--82}, title = {Detection and Correction of Malicious and Natural Faults in Cryptographic Modules}, url = {http://www.easychair.org/publications/paper/zMjh}, year = 2018 }
  Link
  http://www.easychair.org/publications/paper/zMjh
6. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/mam/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1016/j.micpro.2018.06.009}, journal = {Microprocessors and Microsystems - Embedded Hardware Design}, pages = {316--326}, title = {S-box-based random number generation for stochastic computing}, url = {https://doi.org/10.1016/j.micpro.2018.06.009}, volume = 61, year = 2018 }
  Link
  https://doi.org/10.1016/j.micpro.2018.06.009
7. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dcis/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Mael and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Conference on Design of Circuits and Integrated Systems, {DCIS} 2018, Lyon, France, November 14-16, 2018}, crossref = {DBLP:conf/dcis/2018}, doi = {10.1109/DCIS.2018.8681476}, pages = {1--6}, title = {Security-oriented Code-based Architectures for Mitigating Fault Attacks}, url = {https://doi.org/10.1109/DCIS.2018.8681476}, year = 2018 }
  Link
  https://doi.org/10.1109/DCIS.2018.8681476
8. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewme/PolianG18, abteilung = {hocos}, author = {Polian, Ilia and Gay, Mael}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {12th European Workshop on Microelectronics Education, {EWME} 2018, Braunschweig, Germany, September 24-26, 2018}, crossref = {DBLP:conf/ewme/2018}, doi = {10.1109/EWME.2018.8629483}, pages = {59--62}, title = {Hardware-oriented Security in a Computer Science Curriculum}, url = {https://doi.org/10.1109/EWME.2018.8629483}, year = 2018 }
  Link
  https://doi.org/10.1109/EWME.2018.8629483
9. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/samos/RegazzoniFP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Fowler, Austin G. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018.}, crossref = {DBLP:conf/samos/2018}, doi = {10.1145/3229631.3264737}, pages = {173--178}, title = {Quantum era challenges for classical computers}, url = {https://doi.org/10.1145/3229631.3264737}, year = 2018 }
  Link
  https://doi.org/10.1145/3229631.3264737
10. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/RegazzoniAP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Alippi, Cesare and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the International Conference on Computer-Aided Design, {ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018}, crossref = {DBLP:conf/iccad/2018}, doi = {10.1145/3240765.3243497}, pages = 44, title = {Security: the dark side of approximate computing?}, url = {https://doi.org/10.1145/3240765.3243497}, year = 2018 }
  Link
  https://doi.org/10.1145/3240765.3243497
11. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jetc/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/3183345}, journal = {{JETC}}, number = 2, pages = {31:1--31:21}, title = {Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design}, url = {https://doi.org/10.1145/3183345}, volume = 14, year = 2018 }
  Link
  https://doi.org/10.1145/3183345
12. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/esl/Polian18, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/LES.2017.2754446}, journal = {Embedded Systems Letters}, number = 1, pages = {26--29}, title = {Test and Reliability Challenges for Approximate Circuitry}, url = {https://doi.org/10.1109/LES.2017.2754446}, volume = 10, year = 2018 }
  Link
  https://doi.org/10.1109/LES.2017.2754446
13. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dcis/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Mael and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Conference on Design of Circuits and Integrated Systems, {DCIS} 2018, Lyon, France, November 14-16, 2018}, crossref = {DBLP:conf/dcis/2018}, doi = {10.1109/DCIS.2018.8681476}, pages = {1--6}, title = {Security-oriented Code-based Architectures for Mitigating Fault Attacks}, url = {https://doi.org/10.1109/DCIS.2018.8681476}, year = 2018 }
  Link
  https://doi.org/10.1109/DCIS.2018.8681476
14. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/RegazzoniAP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Alippi, Cesare and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the International Conference on Computer-Aided Design, {ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018}, crossref = {DBLP:conf/iccad/2018}, doi = {10.1145/3240765.3243497}, pages = 44, title = {Security: the dark side of approximate computing?}, url = {https://doi.org/10.1145/3240765.3243497}, year = 2018 }
  Link
  https://doi.org/10.1145/3240765.3243497
15. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ches/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Ma{\"{e}}l and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{PROOFS} 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with {CHES} 2018, Amsterdam, The Netherlands, September 13, 2018}, crossref = {DBLP:conf/ches/2018proofs}, pages = {68--82}, title = {Detection and Correction of Malicious and Natural Faults in Cryptographic Modules}, url = {http://www.easychair.org/publications/paper/zMjh}, year = 2018 }
  Link
  http://www.easychair.org/publications/paper/zMjh
16. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jetc/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/3183345}, journal = {{JETC}}, number = 2, pages = {31:1--31:21}, title = {Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design}, url = {https://doi.org/10.1145/3183345}, volume = 14, year = 2018 }
  Link
  https://doi.org/10.1145/3183345
2017
1. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/BurchardGEH00KP17, abteilung = {hocos}, author = {Burchard, Jan and Gay, Mael and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2017, Taipei, Taiwan, September 25, 2017}, crossref = {DBLP:conf/fdtc/2017}, doi = {10.1109/FDTC.2017.13}, pages = {65--72}, title = {AutoFault: Towards Automatic Construction of Algebraic Fault Attacks}, url = {https://doi.org/10.1109/FDTC.2017.13}, year = 2017 }
  Link
  https://doi.org/10.1109/FDTC.2017.13
2. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7926949}, pages = {1--6}, title = {Framework for quantifying and managing accuracy in stochastic circuit design}, url = {https://doi.org/10.23919/DATE.2017.7926949}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7926949
3. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherHP17, abteilung = {hocos}, author = {Kinseher, Josef and Heis, Leonhard and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927106}, pages = {852--857}, title = {Analyzing the effects of peripheral circuit aging of embedded {SRAM} architectures}, url = {https://doi.org/10.23919/DATE.2017.7927106}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927106
4. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/socc/PolianRS17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco and Sep{\'{u}}lveda, Johanna}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017, Munich, Germany, September 5-8, 2017}, crossref = {DBLP:conf/socc/2017}, doi = {10.1109/SOCC.2017.8226017}, pages = {102--107}, title = {Introduction to hardware-oriented security for MPSoCs}, url = {https://doi.org/10.1109/SOCC.2017.8226017}, year = 2017 }
  Link
  https://doi.org/10.1109/SOCC.2017.8226017
5. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherHP17, abteilung = {hocos}, author = {Kinseher, Josef and Heis, Leonhard and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927106}, pages = {852--857}, title = {Analyzing the effects of peripheral circuit aging of embedded {SRAM} architectures}, url = {https://doi.org/10.23919/DATE.2017.7927106}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927106
6. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7926949}, pages = {1--6}, title = {Framework for quantifying and managing accuracy in stochastic circuit design}, url = {https://doi.org/10.23919/DATE.2017.7926949}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7926949
7. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/RegazzoniP17, abteilung = {hocos}, author = {Regazzoni, Francesco and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC} 2017, Chiba, Japan, January 16-19, 2017}, crossref = {DBLP:conf/aspdac/2017}, doi = {10.1109/ASPDAC.2017.7858319}, pages = {194--199}, title = {Securing the hardware of cyber-physical systems}, url = {https://doi.org/10.1109/ASPDAC.2017.7858319}, year = 2017 }
  Link
  https://doi.org/10.1109/ASPDAC.2017.7858319
8. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianR17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd {IEEE} European Test Symposium, {ETS} 2017, Limassol, Cyprus, May 22-26, 2017}, crossref = {DBLP:conf/ets/2017}, doi = {10.1109/ETS.2017.7968230}, pages = {1--10}, title = {Counteracting malicious faults in cryptographic circuits}, url = {https://doi.org/10.1109/ETS.2017.7968230}, year = 2017 }
  Link
  https://doi.org/10.1109/ETS.2017.7968230
9. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ivsw/BurchardEHG0SKP17, abteilung = {hocos}, author = {Burchard, Jan and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Gay, Mael and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} 2nd International Verification and Security Workshop, {IVSW} 2017, Thessaloniki, Greece, July 3-5, 2017}, crossref = {DBLP:conf/ivsw/2017}, doi = {10.1109/IVSW.2017.8031537}, pages = {7--12}, title = {Towards mixed structural-functional models for algebraic fault attacks on ciphers}, url = {https://doi.org/10.1109/IVSW.2017.8031537}, year = 2017 }
  Link
  https://doi.org/10.1109/IVSW.2017.8031537
10. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRF0RP17, abteilung = {hocos}, author = {Sauer, Matthias and Raiola, Pascal and Feiten, Linus and Becker, Bernd and R{\"{u}}hrmair, Ulrich and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927076}, pages = {680--685}, title = {Sensitized path {PUF:} {A} lightweight embedded physical unclonable function}, url = {https://doi.org/10.23919/DATE.2017.7927076}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927076
11. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianR17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd {IEEE} European Test Symposium, {ETS} 2017, Limassol, Cyprus, May 22-26, 2017}, crossref = {DBLP:conf/ets/2017}, doi = {10.1109/ETS.2017.7968230}, pages = {1--10}, title = {Counteracting malicious faults in cryptographic circuits}, url = {https://doi.org/10.1109/ETS.2017.7968230}, year = 2017 }
  Link
  https://doi.org/10.1109/ETS.2017.7968230
12. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsd/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Euromicro Conference on Digital System Design, {DSD} 2017, Vienna, Austria, August 30 - Sept. 1, 2017}, crossref = {DBLP:conf/dsd/2017}, doi = {10.1109/DSD.2017.29}, pages = {1--8}, title = {Building a Better Random Number Generator for Stochastic Computing}, url = {https://doi.org/10.1109/DSD.2017.29}, year = 2017 }
  Link
  https://doi.org/10.1109/DSD.2017.29
13. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/socc/PolianRS17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco and Sep{\'{u}}lveda, Johanna}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017, Munich, Germany, September 5-8, 2017}, crossref = {DBLP:conf/socc/2017}, doi = {10.1109/SOCC.2017.8226017}, pages = {102--107}, title = {Introduction to hardware-oriented security for MPSoCs}, url = {https://doi.org/10.1109/SOCC.2017.8226017}, year = 2017 }
  Link
  https://doi.org/10.1109/SOCC.2017.8226017
14. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/BurchardGEH00KP17, abteilung = {hocos}, author = {Burchard, Jan and Gay, Mael and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2017, Taipei, Taiwan, September 25, 2017}, crossref = {DBLP:conf/fdtc/2017}, doi = {10.1109/FDTC.2017.13}, pages = {65--72}, title = {AutoFault: Towards Automatic Construction of Algebraic Fault Attacks}, url = {https://doi.org/10.1109/FDTC.2017.13}, year = 2017 }
  Link
  https://doi.org/10.1109/FDTC.2017.13
15. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsd/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Euromicro Conference on Digital System Design, {DSD} 2017, Vienna, Austria, August 30 - Sept. 1, 2017}, crossref = {DBLP:conf/dsd/2017}, doi = {10.1109/DSD.2017.29}, pages = {1--8}, title = {Building a Better Random Number Generator for Stochastic Computing}, url = {https://doi.org/10.1109/DSD.2017.29}, year = 2017 }
  Link
  https://doi.org/10.1109/DSD.2017.29
16. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/RegazzoniP17, abteilung = {hocos}, author = {Regazzoni, Francesco and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC} 2017, Chiba, Japan, January 16-19, 2017}, crossref = {DBLP:conf/aspdac/2017}, doi = {10.1109/ASPDAC.2017.7858319}, pages = {194--199}, title = {Securing the hardware of cyber-physical systems}, url = {https://doi.org/10.1109/ASPDAC.2017.7858319}, year = 2017 }
  Link
  https://doi.org/10.1109/ASPDAC.2017.7858319
17. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRF0RP17, abteilung = {hocos}, author = {Sauer, Matthias and Raiola, Pascal and Feiten, Linus and Becker, Bernd and R{\"{u}}hrmair, Ulrich and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927076}, pages = {680--685}, title = {Sensitized path {PUF:} {A} lightweight embedded physical unclonable function}, url = {https://doi.org/10.23919/DATE.2017.7927076}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927076
18. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ivsw/BurchardEHG0SKP17, abteilung = {hocos}, author = {Burchard, Jan and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Gay, Mael and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} 2nd International Verification and Security Workshop, {IVSW} 2017, Thessaloniki, Greece, July 3-5, 2017}, crossref = {DBLP:conf/ivsw/2017}, doi = {10.1109/IVSW.2017.8031537}, pages = {7--12}, title = {Towards mixed structural-functional models for algebraic fault attacks on ciphers}, url = {https://doi.org/10.1109/IVSW.2017.8031537}, year = 2017 }
  Link
  https://doi.org/10.1109/IVSW.2017.8031537
2016
1. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tc/SauerBP16, abteilung = {hocos}, author = {Sauer, Matthias and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TC.2015.2458869}, journal = {{IEEE} Trans. Computers}, number = 6, pages = {1869--1881}, title = {{PHAETON:} {A} SAT-Based Framework for Timing-Aware Path Sensitization}, url = {https://doi.org/10.1109/TC.2015.2458869}, volume = 65, year = 2016 }
  Link
  https://doi.org/10.1109/TC.2015.2458869
2. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wsa/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{WSA} 2016, 20th International {ITG} Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016.}, crossref = {DBLP:conf/wsa/2016}, pages = {1--8}, title = {Detection Performance of {MIMO} Unique Word {OFDM}}, url = {http://ieeexplore.ieee.org/document/7499144/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7499144/
3. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/eusipco/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th European Signal Processing Conference, {EUSIPCO} 2016, Budapest, Hungary, August 29 - September 2, 2016}, crossref = {DBLP:conf/eusipco/2016}, doi = {10.1109/EUSIPCO.2016.7760523}, pages = {1623--1627}, title = {Memory error resilient detection for massive {MIMO} systems}, url = {https://doi.org/10.1109/EUSIPCO.2016.7760523}, year = 2016 }
  Link
  https://doi.org/10.1109/EUSIPCO.2016.7760523
4. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/KinseherVZP16, abteilung = {hocos}, author = {Kinseher, Josef and V{\"{o}}lker, Moritz and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21th {IEEE} European Test Symposium, {ETS} 2016, Amsterdam, Netherlands, May 23-27, 2016}, crossref = {DBLP:conf/ets/2016}, doi = {10.1109/ETS.2016.7519324}, pages = {1--2}, title = {Failure mechanisms and test methods for the {SRAM} {TVC} write-assist technique}, url = {https://doi.org/10.1109/ETS.2016.7519324}, year = 2016 }
  Link
  https://doi.org/10.1109/ETS.2016.7519324
5. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherZPL16, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia and Leininger, Andreas}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016}, crossref = {DBLP:conf/date/2016}, pages = {984--989}, title = {Improving {SRAM} test quality by leveraging self-timed circuits}, url = {http://ieeexplore.ieee.org/document/7459450/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7459450/
6. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJRMWBP16, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Reimer, Sven and Miyase, Kohei and Wen, Xiaoqing and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {25th {IEEE} Asian Test Symposium, {ATS} 2016, Hiroshima, Japan, November 21-24, 2016}, crossref = {DBLP:conf/ats/2016}, doi = {10.1109/ATS.2016.63}, pages = {179--184}, title = {On Optimal Power-Aware Path Sensitization}, url = {https://doi.org/10.1109/ATS.2016.63}, year = 2016 }
  Link
  https://doi.org/10.1109/ATS.2016.63
7. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dagstuhl-reports/KerenPT16, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia and Tehranipoor, Mark M.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.4230/DagRep.6.5.72}, journal = {Dagstuhl Reports}, number = 5, pages = {72--93}, title = {Hardware Security (Dagstuhl Seminar 16202)}, url = {https://doi.org/10.4230/DagRep.6.5.72}, volume = 6, year = 2016 }
  Link
  https://doi.org/10.4230/DagRep.6.5.72
8. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJRMWBP16, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Reimer, Sven and Miyase, Kohei and Wen, Xiaoqing and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {25th {IEEE} Asian Test Symposium, {ATS} 2016, Hiroshima, Japan, November 21-24, 2016}, crossref = {DBLP:conf/ats/2016}, doi = {10.1109/ATS.2016.63}, pages = {179--184}, title = {On Optimal Power-Aware Path Sensitization}, url = {https://doi.org/10.1109/ATS.2016.63}, year = 2016 }
  Link
  https://doi.org/10.1109/ATS.2016.63
9. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherZPL16, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia and Leininger, Andreas}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016}, crossref = {DBLP:conf/date/2016}, pages = {984--989}, title = {Improving {SRAM} test quality by leveraging self-timed circuits}, url = {http://ieeexplore.ieee.org/document/7459450/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7459450/
10. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wsa/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{WSA} 2016, 20th International {ITG} Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016.}, crossref = {DBLP:conf/wsa/2016}, pages = {1--8}, title = {Detection Performance of {MIMO} Unique Word {OFDM}}, url = {http://ieeexplore.ieee.org/document/7499144/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7499144/
11. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/eusipco/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th European Signal Processing Conference, {EUSIPCO} 2016, Budapest, Hungary, August 29 - September 2, 2016}, crossref = {DBLP:conf/eusipco/2016}, doi = {10.1109/EUSIPCO.2016.7760523}, pages = {1623--1627}, title = {Memory error resilient detection for massive {MIMO} systems}, url = {https://doi.org/10.1109/EUSIPCO.2016.7760523}, year = 2016 }
  Link
  https://doi.org/10.1109/EUSIPCO.2016.7760523
12. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dagstuhl-reports/KerenPT16, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia and Tehranipoor, Mark M.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.4230/DagRep.6.5.72}, journal = {Dagstuhl Reports}, number = 5, pages = {72--93}, title = {Hardware Security (Dagstuhl Seminar 16202)}, url = {https://doi.org/10.4230/DagRep.6.5.72}, volume = 6, year = 2016 }
  Link
  https://doi.org/10.4230/DagRep.6.5.72
13. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tc/SauerBP16, abteilung = {hocos}, author = {Sauer, Matthias and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TC.2015.2458869}, journal = {{IEEE} Trans. Computers}, number = 6, pages = {1869--1881}, title = {{PHAETON:} {A} SAT-Based Framework for Timing-Aware Path Sensitization}, url = {https://doi.org/10.1109/TC.2015.2458869}, volume = 65, year = 2016 }
  Link
  https://doi.org/10.1109/TC.2015.2458869
14. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/KinseherVZP16, abteilung = {hocos}, author = {Kinseher, Josef and V{\"{o}}lker, Moritz and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21th {IEEE} European Test Symposium, {ETS} 2016, Amsterdam, Netherlands, May 23-27, 2016}, crossref = {DBLP:conf/ets/2016}, doi = {10.1109/ETS.2016.7519324}, pages = {1--2}, title = {Failure mechanisms and test methods for the {SRAM} {TVC} write-assist technique}, url = {https://doi.org/10.1109/ETS.2016.7519324}, year = 2016 }
  Link
  https://doi.org/10.1109/ETS.2016.7519324
2015
1. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/KinseherZP15, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November 22-25, 2015}, crossref = {DBLP:conf/ats/2015}, doi = {10.1109/ATS.2015.18}, pages = {61--66}, title = {On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs}, url = {https://doi.org/10.1109/ATS.2015.18}, year = 2015 }
  Link
  https://doi.org/10.1109/ATS.2015.18
2. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerPND15, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Nemoto, Kae and Devitt, Simon J.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 7th International Conference, {RC} 2015,Grenoble, France, July 16-17, 2015, Proceedings}, crossref = {DBLP:conf/rc/2015}, doi = {10.1007/978-3-319-20860-2_9}, pages = {139--154}, title = {A Fully Fault-Tolerant Representation of Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-20860-2_9}, year = 2015 }
  Link
  https://doi.org/10.1007/978-3-319-20860-2_9
3. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dac/PolianF15, abteilung = {hocos}, author = {Polian, Ilia and Fowler, Austin G.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015}, crossref = {DBLP:conf/dac/2015}, doi = {10.1145/2744769.2747921}, pages = {61:1--61:6}, title = {Design automation challenges for scalable quantum architectures}, url = {https://doi.org/10.1145/2744769.2747921}, year = 2015 }
  Link
  https://doi.org/10.1145/2744769.2747921
4. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JovanovicP15, abteilung = {hocos}, author = {Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March 9-13, 2015}, crossref = {DBLP:conf/date/2015}, pages = {601--604}, title = {Fault-based attacks on the Bel-T block cipher family}, url = {http://dl.acm.org/citation.cfm?id=2755889}, year = 2015 }
  Link
  http://dl.acm.org/citation.cfm?id=2755889
5. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dac/PolianF15, abteilung = {hocos}, author = {Polian, Ilia and Fowler, Austin G.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015}, crossref = {DBLP:conf/dac/2015}, doi = {10.1145/2744769.2747921}, pages = {61:1--61:6}, title = {Design automation challenges for scalable quantum architectures}, url = {https://doi.org/10.1145/2744769.2747921}, year = 2015 }
  Link
  https://doi.org/10.1145/2744769.2747921
6. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerPND15, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Nemoto, Kae and Devitt, Simon J.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 7th International Conference, {RC} 2015,Grenoble, France, July 16-17, 2015, Proceedings}, crossref = {DBLP:conf/rc/2015}, doi = {10.1007/978-3-319-20860-2_9}, pages = {139--154}, title = {A Fully Fault-Tolerant Representation of Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-20860-2_9}, year = 2015 }
  Link
  https://doi.org/10.1007/978-3-319-20860-2_9
7. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/FeitenSSTPB15, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Tomashevich, Victor and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2015.2448687}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 8, pages = {1358--1369}, title = {Formal Vulnerability Analysis of Security Components}, url = {https://doi.org/10.1109/TCAD.2015.2448687}, volume = 34, year = 2015 }
  Link
  https://doi.org/10.1109/TCAD.2015.2448687
8. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/KinseherZP15, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November 22-25, 2015}, crossref = {DBLP:conf/ats/2015}, doi = {10.1109/ATS.2015.18}, pages = {61--66}, title = {On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs}, url = {https://doi.org/10.1109/ATS.2015.18}, year = 2015 }
  Link
  https://doi.org/10.1109/ATS.2015.18
9. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/FeitenSSTPB15, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Tomashevich, Victor and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2015.2448687}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 8, pages = {1358--1369}, title = {Formal Vulnerability Analysis of Security Components}, url = {https://doi.org/10.1109/TCAD.2015.2448687}, volume = 34, year = 2015 }
  Link
  https://doi.org/10.1109/TCAD.2015.2448687
10. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JovanovicP15, abteilung = {hocos}, author = {Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March 9-13, 2015}, crossref = {DBLP:conf/date/2015}, pages = {601--604}, title = {Fault-based attacks on the Bel-T block cipher family}, url = {http://dl.acm.org/citation.cfm?id=2755889}, year = 2015 }
  Link
  http://dl.acm.org/citation.cfm?id=2755889
2014
1. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 783, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {http://eprint.iacr.org/2014/783}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/783
2. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/UppuUSP14, abteilung = {hocos}, author = {Uppu, Ravi Kanth and Uppu, Ravi Tej and Singh, Adit D. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.30}, pages = {133--138}, title = {Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths}, url = {https://doi.org/10.1109/VLSID.2014.30}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.30
3. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/TomashevichGFWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Fesl, Christian and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2014, Warsaw, Poland, 23-25 April, 2014}, crossref = {DBLP:conf/ddecs/2014}, doi = {10.1109/DDECS.2014.6868800}, pages = {246--249}, title = {A new architecture for minimum mean square error sorted {QR} decomposition for {MIMO} wireless communication systems}, url = {https://doi.org/10.1109/DDECS.2014.6868800}, year = 2014 }
  Link
  https://doi.org/10.1109/DDECS.2014.6868800
4. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2014, Dresden, Germany, March 24-28, 2014}, crossref = {DBLP:conf/date/2014}, doi = {10.7873/DATE.2014.137}, pages = {1--4}, title = {Software-based Pauli tracking in fault-tolerant quantum circuits}, url = {https://doi.org/10.7873/DATE.2014.137}, year = 2014 }
  Link
  https://doi.org/10.7873/DATE.2014.137
5. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerPIMSCWB14, abteilung = {hocos}, author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans{-}Joachim and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847806}, pages = {1--6}, title = {Variation-aware deterministic {ATPG}}, url = {https://doi.org/10.1109/ETS.2014.6847806}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847806
6. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iet-cdt/PolianT14, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mark Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1049/iet-cdt.2014.0194}, journal = {{IET} Computers {\&} Digital Techniques}, number = 6, pages = {237--238}, title = {Guest Editorial}, url = {https://doi.org/10.1049/iet-cdt.2014.0194}, volume = 8, year = 2014 }
  Link
  https://doi.org/10.1049/iet-cdt.2014.0194
7. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} 20th International On-Line Testing Symposium, {IOLTS} 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014}, crossref = {DBLP:conf/iolts/2014}, doi = {10.1109/IOLTS.2014.6873670}, pages = {43--48}, title = {Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis}, url = {https://doi.org/10.1109/IOLTS.2014.6873670}, year = 2014 }
  Link
  https://doi.org/10.1109/IOLTS.2014.6873670
8. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/TomashevichNKKP14, abteilung = {hocos}, author = {Tomashevich, Victor and Neumeier, Yaara and Kumar, Raghavan and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2014, Amsterdam, The Netherlands, October 1-3, 2014}, crossref = {DBLP:conf/dft/2014}, doi = {10.1109/DFT.2014.6962084}, pages = {40--45}, title = {Protecting cryptographic hardware against malicious attacks by nonlinear robust codes}, url = {https://doi.org/10.1109/DFT.2014.6962084}, year = 2014 }
  Link
  https://doi.org/10.1109/DFT.2014.6962084
9. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
  - BibTeX
  - Link
  BibTeX
  @book{StephGI2014, abteilung = {hocos}, address = {Berlin, Boston}, author = {Eggersglüß, Stephan and Fey, Görschwin and Polian, Ilia}, issn = {978-3-486-99073-7}, language = {DT}, owner = {haefneht}, publisher = {De Gruyter Oldenbourg}, title = {Test digitaler Schaltkreise}, url = {https://www.degruyter.com/view/product/214529}, year = 2014 }
  Link
  https://www.degruyter.com/view/product/214529
10. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianJS14, abteilung = {hocos}, author = {Polian, Ilia and Jiang, Jie and Singh, Adit D.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847794}, pages = {1--6}, title = {Detection conditions for errors in self-adaptive better-than-worst-case designs}, url = {https://doi.org/10.1109/ETS.2014.6847794}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847794
11. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2014, Dresden, Germany, March 24-28, 2014}, crossref = {DBLP:conf/date/2014}, doi = {10.7873/DATE.2014.137}, pages = {1--4}, title = {Software-based Pauli tracking in fault-tolerant quantum circuits}, url = {https://doi.org/10.7873/DATE.2014.137}, year = 2014 }
  Link
  https://doi.org/10.7873/DATE.2014.137
12. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
  - BibTeX
  - Link
  BibTeX
  @book{StephGI2014, abteilung = {hocos}, address = {Berlin, Boston}, author = {Eggersglüß, Stephan and Fey, Görschwin and Polian, Ilia}, issn = {978-3-486-99073-7}, language = {DT}, owner = {haefneht}, publisher = {De Gruyter Oldenbourg}, title = {Test digitaler Schaltkreise}, url = {https://www.degruyter.com/view/product/214529}, year = 2014 }
  Link
  https://www.degruyter.com/view/product/214529
13. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wisee/TomashevichGWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014}, crossref = {DBLP:conf/wisee/2014}, doi = {10.1109/WiSEE.2014.6973066}, pages = {1--6}, title = {Reliability analysis of {MIMO} channel preprocessing by fault injection}, url = {https://doi.org/10.1109/WiSEE.2014.6973066}, year = 2014 }
  Link
  https://doi.org/10.1109/WiSEE.2014.6973066
14. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,Kyoto, Japan, July 10-11, 2014. Proceedings}, crossref = {DBLP:conf/rc/2014}, doi = {10.1007/978-3-319-08494-7_15}, pages = {189--200}, title = {Cross-Level Validation of Topological Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-08494-7_15}, year = 2014 }
  Link
  https://doi.org/10.1007/978-3-319-08494-7_15
15. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian14, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1515/itit-2013-1038}, journal = {it - Information Technology}, number = 4, pages = {192--202}, title = {Hardware security and test: Friends or enemies?}, url = {https://doi.org/10.1515/itit-2013-1038}, volume = 56, year = 2014 }
  Link
  https://doi.org/10.1515/itit-2013-1038
16. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,Kyoto, Japan, July 10-11, 2014. Proceedings}, crossref = {DBLP:conf/rc/2014}, doi = {10.1007/978-3-319-08494-7_15}, pages = {189--200}, title = {Cross-Level Validation of Topological Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-08494-7_15}, year = 2014 }
  Link
  https://doi.org/10.1007/978-3-319-08494-7_15
17. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/TomashevichGFWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Fesl, Christian and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2014, Warsaw, Poland, 23-25 April, 2014}, crossref = {DBLP:conf/ddecs/2014}, doi = {10.1109/DDECS.2014.6868800}, pages = {246--249}, title = {A new architecture for minimum mean square error sorted {QR} decomposition for {MIMO} wireless communication systems}, url = {https://doi.org/10.1109/DDECS.2014.6868800}, year = 2014 }
  Link
  https://doi.org/10.1109/DDECS.2014.6868800
18. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 782, title = {Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis}, url = {http://eprint.iacr.org/2014/782}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/782
19. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroRPB14, abteilung = {hocos}, author = {Czutro, Alexander and Reddy, Sudhakar M. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.17}, pages = {56--61}, title = {SAT-Based Test Pattern Generation with Improved Dynamic Compaction}, url = {https://doi.org/10.1109/VLSID.2014.17}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.17
20. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/TomashevichNKKP14, abteilung = {hocos}, author = {Tomashevich, Victor and Neumeier, Yaara and Kumar, Raghavan and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2014, Amsterdam, The Netherlands, October 1-3, 2014}, crossref = {DBLP:conf/dft/2014}, doi = {10.1109/DFT.2014.6962084}, pages = {40--45}, title = {Protecting cryptographic hardware against malicious attacks by nonlinear robust codes}, url = {https://doi.org/10.1109/DFT.2014.6962084}, year = 2014 }
  Link
  https://doi.org/10.1109/DFT.2014.6962084
21. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iet-cdt/PolianT14, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mark Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1049/iet-cdt.2014.0194}, journal = {{IET} Computers {\&} Digital Techniques}, number = 6, pages = {237--238}, title = {Guest Editorial}, url = {https://doi.org/10.1049/iet-cdt.2014.0194}, volume = 8, year = 2014 }
  Link
  https://doi.org/10.1049/iet-cdt.2014.0194
22. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerPIMSCWB14, abteilung = {hocos}, author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans{-}Joachim and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847806}, pages = {1--6}, title = {Variation-aware deterministic {ATPG}}, url = {https://doi.org/10.1109/ETS.2014.6847806}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847806
23. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/UppuUSP14, abteilung = {hocos}, author = {Uppu, Ravi Kanth and Uppu, Ravi Tej and Singh, Adit D. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.30}, pages = {133--138}, title = {Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths}, url = {https://doi.org/10.1109/VLSID.2014.30}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.30
24. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian14, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1515/itit-2013-1038}, journal = {it - Information Technology}, number = 4, pages = {192--202}, title = {Hardware security and test: Friends or enemies?}, url = {https://doi.org/10.1515/itit-2013-1038}, volume = 56, year = 2014 }
  Link
  https://doi.org/10.1515/itit-2013-1038
25. Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ETS.2014.6847806
  Zusammenfassung
  In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.
  BibTeX
  @inproceedings{SauerPIMSCWB2014, abstract = {In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.}, abteilung = {ra; award}, address = {Paderborn, Germany}, author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans-Joachim and Becker, Bernd}, award = {Best paper award}, booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)}, comment = {Paper 08A-2IEEE Catalog Number CFP14216-USBISBN 978-1-4799-3414-0ISBN 978-1-4799-3415-7}, day = {26--30}, doi = {10.1109/ETS.2014.6847806}, location = {Paderborn, Germany}, month = {05}, owner = {imhofml}, pages = {87--92}, privnote = {Paper 08A-2 IEEE Catalog Number CFP14216-USB ISBN 978-1-4799-3414-0 ISBN 978-1-4799-3415-7}, project = {REALTEST; OASIS ; NotAckREAL}, title = {{Variation-Aware Deterministic ATPG}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_SauerPIMSCWB2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_SauerPIMSCWB2014.pdf
26. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 783, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {http://eprint.iacr.org/2014/783}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/783
27. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2014, Busan, South Korea, September 23, 2014}, crossref = {DBLP:conf/fdtc/2014}, doi = {10.1109/FDTC.2014.12}, pages = {18--28}, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {https://doi.org/10.1109/FDTC.2014.12}, year = 2014 }
  Link
  https://doi.org/10.1109/FDTC.2014.12
28. Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ETS.2014.6847806
  Zusammenfassung
  In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.
  BibTeX
  @inproceedings{SauerPIMSCWB2014, abstract = {In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.}, abteilung = {ra; award}, address = {Paderborn, Germany}, author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans-Joachim and Becker, Bernd}, award = {Best paper award}, booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)}, comment = {Paper 08A-2IEEE Catalog Number CFP14216-USBISBN 978-1-4799-3414-0ISBN 978-1-4799-3415-7}, day = {26--30}, doi = {10.1109/ETS.2014.6847806}, location = {Paderborn, Germany}, month = {05}, owner = {imhofml}, pages = {87--92}, project = {REALTEST; OASIS ; NotAckREAL}, title = {{Variation-Aware Deterministic ATPG}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_SauerPIMSCWB2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_SauerPIMSCWB2014.pdf
29. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wisee/TomashevichGWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014}, crossref = {DBLP:conf/wisee/2014}, doi = {10.1109/WiSEE.2014.6973066}, pages = {1--6}, title = {Reliability analysis of {MIMO} channel preprocessing by fault injection}, url = {https://doi.org/10.1109/WiSEE.2014.6973066}, year = 2014 }
  Link
  https://doi.org/10.1109/WiSEE.2014.6973066
30. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 782, title = {Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis}, url = {http://eprint.iacr.org/2014/782}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/782
31. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2014, Busan, South Korea, September 23, 2014}, crossref = {DBLP:conf/fdtc/2014}, doi = {10.1109/FDTC.2014.12}, pages = {18--28}, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {https://doi.org/10.1109/FDTC.2014.12}, year = 2014 }
  Link
  https://doi.org/10.1109/FDTC.2014.12
32. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroRPB14, abteilung = {hocos}, author = {Czutro, Alexander and Reddy, Sudhakar M. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.17}, pages = {56--61}, title = {SAT-Based Test Pattern Generation with Improved Dynamic Compaction}, url = {https://doi.org/10.1109/VLSID.2014.17}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.17
33. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianJS14, abteilung = {hocos}, author = {Polian, Ilia and Jiang, Jie and Singh, Adit D.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847794}, pages = {1--6}, title = {Detection conditions for errors in self-adaptive better-than-worst-case designs}, url = {https://doi.org/10.1109/ETS.2014.6847794}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847794
34. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} 20th International On-Line Testing Symposium, {IOLTS} 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014}, crossref = {DBLP:conf/iolts/2014}, doi = {10.1109/IOLTS.2014.6873670}, pages = {43--48}, title = {Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis}, url = {https://doi.org/10.1109/IOLTS.2014.6873670}, year = 2014 }
  Link
  https://doi.org/10.1109/IOLTS.2014.6873670
2013
1. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PalerKPH13, abteilung = {hocos}, author = {Paler, Alexandru and Kinseher, Josef and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2013 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City, NY, USA, October 2-4, 2013}, crossref = {DBLP:conf/dft/2013}, doi = {10.1109/DFT.2013.6653589}, pages = {95--100}, title = {Approximate simulation of circuits with probabilistic behavior}, url = {https://doi.org/10.1109/DFT.2013.6653589}, year = 2013 }
  Link
  https://doi.org/10.1109/DFT.2013.6653589
2. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianK13, abteilung = {hocos}, author = {Polian, Ilia and Kreuzer, Martin}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2013, Karlovy Vary, Czech Republic, April 8-10, 2013}, crossref = {DBLP:conf/ddecs/2013}, doi = {10.1109/DDECS.2013.6549781}, pages = {12--17}, title = {Fault-based attacks on cryptographic hardware}, url = {https://doi.org/10.1109/DDECS.2013.6549781}, year = 2013 }
  Link
  https://doi.org/10.1109/DDECS.2013.6549781
3. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/SauerCSHPB13, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2012.2230297}, journal = {{IEEE} Design {\&} Test}, number = 4, pages = {81--88}, title = {SAT-Based Analysis of Sensitizable Paths}, url = {https://doi.org/10.1109/MDT.2012.2230297}, volume = 30, year = 2013 }
  Link
  https://doi.org/10.1109/MDT.2012.2230297
4. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRSPB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France, March 18-22, 2013}, crossref = {DBLP:conf/date/2013}, doi = {10.7873/DATE.2013.100}, pages = {448--453}, title = {Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths}, url = {https://doi.org/10.7873/DATE.2013.100}, year = 2013 }
  Link
  https://doi.org/10.7873/DATE.2013.100
5. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/JiangACARP13, abteilung = {hocos}, author = {Jiang, J. and Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asian Test Symposium, {ATS} 2013, Yilan County, Taiwan, November 18-21, 2013}, crossref = {DBLP:conf/ats/2013}, doi = {10.1109/ATS.2013.41}, pages = {177--182}, title = {{MIRID:} Mixed-Mode IR-Drop Induced Delay Simulator}, url = {https://doi.org/10.1109/ATS.2013.41}, year = 2013 }
  Link
  https://doi.org/10.1109/ATS.2013.41
6. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianT13, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {31st {IEEE} {VLSI} Test Symposium, {VTS} 2013, Berkeley, CA, USA, April 29 - May 2, 2013}, crossref = {DBLP:conf/vts/2013}, doi = {10.1109/VTS.2013.6548944}, pages = 1, title = {Special session 12A: Hot topic counterfeit {IC} identification: How can test help?}, url = {https://doi.org/10.1109/VTS.2013.6548944}, year = 2013 }
  Link
  https://doi.org/10.1109/VTS.2013.6548944
7. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/JiangACARP13, abteilung = {hocos}, author = {Jiang, J. and Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asian Test Symposium, {ATS} 2013, Yilan County, Taiwan, November 18-21, 2013}, crossref = {DBLP:conf/ats/2013}, doi = {10.1109/ATS.2013.41}, pages = {177--182}, title = {{MIRID:} Mixed-Mode IR-Drop Induced Delay Simulator}, url = {https://doi.org/10.1109/ATS.2013.41}, year = 2013 }
  Link
  https://doi.org/10.1109/ATS.2013.41
8. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/SauerRPSB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Polian, Ilia and Schubert, Tobias and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2013, Yokohama, Japan, January 22-25, 2013}, crossref = {DBLP:conf/aspdac/2013}, doi = {10.1109/ASPDAC.2013.6509651}, pages = {533--539}, title = {Provably optimal test cube generation using quantified boolean formula solving}, url = {https://doi.org/10.1109/ASPDAC.2013.6509651}, year = 2013 }
  Link
  https://doi.org/10.1109/ASPDAC.2013.6509651
9. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/SauerCSHPB13, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2012.2230297}, journal = {{IEEE} Design {\&} Test}, number = 4, pages = {81--88}, title = {SAT-Based Analysis of Sensitizable Paths}, url = {https://doi.org/10.1109/MDT.2012.2230297}, volume = 30, year = 2013 }
  Link
  https://doi.org/10.1109/MDT.2012.2230297
10. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianK13, abteilung = {hocos}, author = {Polian, Ilia and Kreuzer, Martin}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2013, Karlovy Vary, Czech Republic, April 8-10, 2013}, crossref = {DBLP:conf/ddecs/2013}, doi = {10.1109/DDECS.2013.6549781}, pages = {12--17}, title = {Fault-based attacks on cryptographic hardware}, url = {https://doi.org/10.1109/DDECS.2013.6549781}, year = 2013 }
  Link
  https://doi.org/10.1109/DDECS.2013.6549781
11. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/latw/AparicioCARJPB13, abteilung = {hocos}, author = {Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Jiang, J. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Latin American Test Workshop, {LATW} 2013, Cordoba, Argentina, 3-5 April, 2013}, crossref = {DBLP:conf/latw/2013}, doi = {10.1109/LATW.2013.6562657}, pages = {1--6}, title = {Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays}, url = {https://doi.org/10.1109/LATW.2013.6562657}, year = 2013 }
  Link
  https://doi.org/10.1109/LATW.2013.6562657
12. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP13, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 778, title = {Multi-Stage Fault Attacks on Block Ciphers}, url = {http://eprint.iacr.org/2013/778}, volume = 2013, year = 2013 }
  Link
  http://eprint.iacr.org/2013/778
13. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP13, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 778, title = {Multi-Stage Fault Attacks on Block Ciphers}, url = {http://eprint.iacr.org/2013/778}, volume = 2013, year = 2013 }
  Link
  http://eprint.iacr.org/2013/778
14. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRSPB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France, March 18-22, 2013}, crossref = {DBLP:conf/date/2013}, doi = {10.7873/DATE.2013.100}, pages = {448--453}, title = {Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths}, url = {https://doi.org/10.7873/DATE.2013.100}, year = 2013 }
  Link
  https://doi.org/10.7873/DATE.2013.100
15. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/latw/AparicioCARJPB13, abteilung = {hocos}, author = {Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Jiang, J. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Latin American Test Workshop, {LATW} 2013, Cordoba, Argentina, 3-5 April, 2013}, crossref = {DBLP:conf/latw/2013}, doi = {10.1109/LATW.2013.6562657}, pages = {1--6}, title = {Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays}, url = {https://doi.org/10.1109/LATW.2013.6562657}, year = 2013 }
  Link
  https://doi.org/10.1109/LATW.2013.6562657
16. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PalerKPH13, abteilung = {hocos}, author = {Paler, Alexandru and Kinseher, Josef and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2013 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City, NY, USA, October 2-4, 2013}, crossref = {DBLP:conf/dft/2013}, doi = {10.1109/DFT.2013.6653589}, pages = {95--100}, title = {Approximate simulation of circuits with probabilistic behavior}, url = {https://doi.org/10.1109/DFT.2013.6653589}, year = 2013 }
  Link
  https://doi.org/10.1109/DFT.2013.6653589
17. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/SauerRPSB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Polian, Ilia and Schubert, Tobias and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2013, Yokohama, Japan, January 22-25, 2013}, crossref = {DBLP:conf/aspdac/2013}, doi = {10.1109/ASPDAC.2013.6509651}, pages = {533--539}, title = {Provably optimal test cube generation using quantified boolean formula solving}, url = {https://doi.org/10.1109/ASPDAC.2013.6509651}, year = 2013 }
  Link
  https://doi.org/10.1109/ASPDAC.2013.6509651
18. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianT13, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {31st {IEEE} {VLSI} Test Symposium, {VTS} 2013, Berkeley, CA, USA, April 29 - May 2, 2013}, crossref = {DBLP:conf/vts/2013}, doi = {10.1109/VTS.2013.6548944}, pages = 1, title = {Special session 12A: Hot topic counterfeit {IC} identification: How can test help?}, url = {https://doi.org/10.1109/VTS.2013.6548944}, year = 2013 }
  Link
  https://doi.org/10.1109/VTS.2013.6548944
2012
1. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
  Zusammenfassung
  An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on GPGPUs. Experiments show that the statistical fault coverage of the generated test sets exceeds by far that achieved by standard approaches.
  BibTeX
  @inproceedings{CzutrIJMSBPW2012, abstract = {An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on GPGPUs. Experiments show that the statistical fault coverage of the generated test sets exceeds by far that achieved by standard approaches.}, abteilung = {ra}, address = {Niigata, Japan}, author = {Czutro, A. and Imhof, Michael E. and Jiang, J. and Mumtaz, Abdullah and Sauer, M. and Becker, Bernd and Polian, Ilia and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 21st IEEE Asian Test Symposium (ATS'12)}, day = {19--22}, doi = {10.1109/ATS.2012.14}, language = {English}, location = {Niigata, Japan}, month = {11}, owner = {Thomas}, pages = {344--349}, project = {REALTEST}, publisher = {IEEE Computer Society}, title = {{Variation-Aware Fault Grading}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ATS_CzutrIJMSBPW2012.pdf}, year = 2012 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ATS_CzutrIJMSBPW2012.pdf
2. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233026}, pages = {1--6}, title = {Multi-conditional {SAT-ATPG} for power-droop testing}, url = {https://doi.org/10.1109/ETS.2012.6233026}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233026
3. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/FeitenSSCBPB12, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Czutro, Alexander and B{\"{o}}hl, Eberhard and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2012, Austin, TX, USA, October 3-5, 2012}, crossref = {DBLP:conf/dft/2012}, doi = {10.1109/DFT.2012.6378198}, pages = {49--54}, title = {{\#}SAT-based vulnerability analysis of security components - {A} case study}, url = {https://doi.org/10.1109/DFT.2012.6378198}, year = 2012 }
  Link
  https://doi.org/10.1109/DFT.2012.6378198
4. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
  - BibTeX
  - Link
  BibTeX
  @inbook{inbook, abteilung = {hocos}, author = {Becker, Bernd and Müller, Günter and Polian, Ilia}, doi = {10.5771/9783845238098-139}, isbn = {9783845238098}, month = {01}, pages = {139-149}, title = {Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society}, url = {https://doi.org/10.5771/9783845238098-139}, year = 2012 }
  Link
  https://doi.org/10.5771/9783845238098-139
5. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerCBP12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233027}, pages = {1--6}, title = {On the quality of test vectors for post-silicon characterization}, url = {https://doi.org/10.1109/ETS.2012.6233027}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233027
6. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/nanoarch/PalerDNP12, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2012 {IEEE/ACM} International Symposium on Nanoscale Architectures, {NANOARCH} 2012, Amsterdam, The Netherlands, July 4-6, 2012}, crossref = {DBLP:conf/nanoarch/2012}, doi = {10.1145/2765491.2765524}, pages = {181--187}, title = {Synthesis of topological quantum circuits}, url = {https://doi.org/10.1145/2765491.2765524}, year = 2012 }
  Link
  https://doi.org/10.1145/2765491.2765524
7. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/SauerKCPRB12, abteilung = {hocos}, author = {Sauer, Matthias and Kupferschmid, Stefan and Czutro, Alexander and Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/itc/2012}, doi = {10.1109/TEST.2012.6401550}, pages = {1--8}, title = {Functional test of small-delay faults using {SAT} and Craig interpolation}, url = {https://doi.org/10.1109/TEST.2012.6401550}, year = 2012 }
  Link
  https://doi.org/10.1109/TEST.2012.6401550
8. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroIJMSBPW12, abteilung = {hocos}, author = {Czutro, Alexander and Imhof, Michael E. and Jiang, J. and Mumtaz, Abdullah and Sauer, Matthias and Becker, Bernd and Polian, Ilia and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.14}, pages = {344--349}, title = {Variation-Aware Fault Grading}, url = {https://doi.org/10.1109/ATS.2012.14}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.14
9. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/SauerCPB12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/iccad/2012}, doi = {10.1145/2429384.2429391}, pages = {30--36}, title = {Small-delay-fault {ATPG} with waveform accuracy}, url = {https://doi.org/10.1145/2429384.2429391}, year = 2012 }
  Link
  https://doi.org/10.1145/2429384.2429391
10. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233026}, pages = {1--6}, title = {Multi-conditional {SAT-ATPG} for power-droop testing}, url = {https://doi.org/10.1109/ETS.2012.6233026}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233026
11. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/SauerKCPRB12, abteilung = {hocos}, author = {Sauer, Matthias and Kupferschmid, Stefan and Czutro, Alexander and Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/itc/2012}, doi = {10.1109/TEST.2012.6401550}, pages = {1--8}, title = {Functional test of small-delay faults using {SAT} and Craig interpolation}, url = {https://doi.org/10.1109/TEST.2012.6401550}, year = 2012 }
  Link
  https://doi.org/10.1109/TEST.2012.6401550
12. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
  - BibTeX
  - Link
  BibTeX
  @inbook{inbook, abteilung = {hocos}, author = {Becker, Bernd and Müller, Günter and Polian, Ilia}, doi = {10.5771/9783845238098-139}, isbn = {9783845238098}, month = {01}, pages = {139-149}, title = {Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society}, url = {https://doi.org/10.5771/9783845238098-139}, year = 2012 }
  Link
  https://doi.org/10.5771/9783845238098-139
13. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 400, title = {An Algebraic Fault Attack on the {LED} Block Cipher}, url = {http://eprint.iacr.org/2012/400}, volume = 2012, year = 2012 }
  Link
  http://eprint.iacr.org/2012/400
14. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/nanoarch/PalerDNP12, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2012 {IEEE/ACM} International Symposium on Nanoscale Architectures, {NANOARCH} 2012, Amsterdam, The Netherlands, July 4-6, 2012}, crossref = {DBLP:conf/nanoarch/2012}, doi = {10.1145/2765491.2765524}, pages = {181--187}, title = {Synthesis of topological quantum circuits}, url = {https://doi.org/10.1145/2765491.2765524}, year = 2012 }
  Link
  https://doi.org/10.1145/2765491.2765524
15. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/cosade/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, {COSADE} 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings}, crossref = {DBLP:conf/cosade/2012}, doi = {10.1007/978-3-642-29912-4_10}, pages = {120--134}, title = {A Fault Attack on the {LED} Block Cipher}, url = {https://doi.org/10.1007/978-3-642-29912-4_10}, year = 2012 }
  Link
  https://doi.org/10.1007/978-3-642-29912-4_10
16. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/Polian12, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.88}, pages = 49, title = {Session Summary {I:} Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking}, url = {https://doi.org/10.1109/ATS.2012.88}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.88
17. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/TomashevichSFP12, abteilung = {hocos}, author = {Tomashevich, Victor and Srinivasan, Sudarshan and Foerg, Fabian and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th {IEEE} International On-Line Testing Symposium, {IOLTS} 2012, Sitges, Spain, June 27-29, 2012}, crossref = {DBLP:conf/iolts/2012}, doi = {10.1109/IOLTS.2012.6313862}, pages = {150--155}, title = {Cross-level protection of circuits against faults and malicious attacks}, url = {https://doi.org/10.1109/IOLTS.2012.6313862}, year = 2012 }
  Link
  https://doi.org/10.1109/IOLTS.2012.6313862
18. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroIJMSBPW12, abteilung = {hocos}, author = {Czutro, Alexander and Imhof, Michael E. and Jiang, J. and Mumtaz, Abdullah and Sauer, Matthias and Becker, Bernd and Polian, Ilia and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.14}, pages = {344--349}, title = {Variation-Aware Fault Grading}, url = {https://doi.org/10.1109/ATS.2012.14}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.14
19. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/PalerPH12, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012}, crossref = {DBLP:conf/aspdac/2012}, doi = {10.1109/ASPDAC.2012.6164942}, pages = {181--186}, title = {Detection and diagnosis of faulty quantum circuits}, url = {https://doi.org/10.1109/ASPDAC.2012.6164942}, year = 2012 }
  Link
  https://doi.org/10.1109/ASPDAC.2012.6164942
20. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JiangSCBP12, abteilung = {hocos}, author = {Jiang, Jie and Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, crossref = {DBLP:conf/date/2012}, doi = {10.1109/DATE.2012.6176507}, pages = {418--423}, title = {On the optimality of {K} longest path generation algorithm under memory constraints}, url = {https://doi.org/10.1109/DATE.2012.6176507}, year = 2012 }
  Link
  https://doi.org/10.1109/DATE.2012.6176507
21. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
  Zusammenfassung
  An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on GPGPUs. Experiments show that the statistical fault coverage of the generated test sets exceeds by far that achieved by standard approaches.
  BibTeX
  @inproceedings{CzutrIJMSBPW2012, abstract = {An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on GPGPUs. Experiments show that the statistical fault coverage of the generated test sets exceeds by far that achieved by standard approaches.}, abteilung = {ra}, address = {Niigata, Japan}, author = {Czutro, A. and Imhof, Michael E. and Jiang, J. and Mumtaz, Abdullah and Sauer, M. and Becker, Bernd and Polian, Ilia and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 21st IEEE Asian Test Symposium (ATS'12)}, day = {19--22}, doi = {10.1109/ATS.2012.14}, language = {English}, location = {Niigata, Japan}, month = {11}, owner = {Thomas}, pages = {344--349}, project = {REALTEST}, publisher = {IEEE Computer Society}, title = {{Variation-Aware Fault Grading}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ATS_CzutrIJMSBPW2012.pdf}, year = 2012 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/ATS_CzutrIJMSBPW2012.pdf
22. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/CzutroSSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} {VLSI} Test Symposium, {VTS} 2012, Maui, Hawaii, USA, 23-26 April 2012}, crossref = {DBLP:conf/vts/2012}, doi = {10.1109/VTS.2012.6231098}, pages = {170--175}, title = {{SAT-ATPG} using preferences for improved detection of complex defect mechanisms}, url = {https://doi.org/10.1109/VTS.2012.6231098}, year = 2012 }
  Link
  https://doi.org/10.1109/VTS.2012.6231098
23. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/PalerPH12, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012}, crossref = {DBLP:conf/aspdac/2012}, doi = {10.1109/ASPDAC.2012.6164942}, pages = {181--186}, title = {Detection and diagnosis of faulty quantum circuits}, url = {https://doi.org/10.1109/ASPDAC.2012.6164942}, year = 2012 }
  Link
  https://doi.org/10.1109/ASPDAC.2012.6164942
24. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/Polian12, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.88}, pages = 49, title = {Session Summary {I:} Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking}, url = {https://doi.org/10.1109/ATS.2012.88}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.88
25. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/cosade/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, {COSADE} 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings}, crossref = {DBLP:conf/cosade/2012}, doi = {10.1007/978-3-642-29912-4_10}, pages = {120--134}, title = {A Fault Attack on the {LED} Block Cipher}, url = {https://doi.org/10.1007/978-3-642-29912-4_10}, year = 2012 }
  Link
  https://doi.org/10.1007/978-3-642-29912-4_10
26. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/FeitenSSCBPB12, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Czutro, Alexander and B{\"{o}}hl, Eberhard and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2012, Austin, TX, USA, October 3-5, 2012}, crossref = {DBLP:conf/dft/2012}, doi = {10.1109/DFT.2012.6378198}, pages = {49--54}, title = {{\#}SAT-based vulnerability analysis of security components - {A} case study}, url = {https://doi.org/10.1109/DFT.2012.6378198}, year = 2012 }
  Link
  https://doi.org/10.1109/DFT.2012.6378198
27. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JiangSCBP12, abteilung = {hocos}, author = {Jiang, Jie and Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, crossref = {DBLP:conf/date/2012}, doi = {10.1109/DATE.2012.6176507}, pages = {418--423}, title = {On the optimality of {K} longest path generation algorithm under memory constraints}, url = {https://doi.org/10.1109/DATE.2012.6176507}, year = 2012 }
  Link
  https://doi.org/10.1109/DATE.2012.6176507
28. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 400, title = {An Algebraic Fault Attack on the {LED} Block Cipher}, url = {http://eprint.iacr.org/2012/400}, volume = 2012, year = 2012 }
  Link
  http://eprint.iacr.org/2012/400
29. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/TomashevichSFP12, abteilung = {hocos}, author = {Tomashevich, Victor and Srinivasan, Sudarshan and Foerg, Fabian and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th {IEEE} International On-Line Testing Symposium, {IOLTS} 2012, Sitges, Spain, June 27-29, 2012}, crossref = {DBLP:conf/iolts/2012}, doi = {10.1109/IOLTS.2012.6313862}, pages = {150--155}, title = {Cross-level protection of circuits against faults and malicious attacks}, url = {https://doi.org/10.1109/IOLTS.2012.6313862}, year = 2012 }
  Link
  https://doi.org/10.1109/IOLTS.2012.6313862
30. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/SauerCPB12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/iccad/2012}, doi = {10.1145/2429384.2429391}, pages = {30--36}, title = {Small-delay-fault {ATPG} with waveform accuracy}, url = {https://doi.org/10.1145/2429384.2429391}, year = 2012 }
  Link
  https://doi.org/10.1145/2429384.2429391
31. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/CzutroSSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} {VLSI} Test Symposium, {VTS} 2012, Maui, Hawaii, USA, 23-26 April 2012}, crossref = {DBLP:conf/vts/2012}, doi = {10.1109/VTS.2012.6231098}, pages = {170--175}, title = {{SAT-ATPG} using preferences for improved detection of complex defect mechanisms}, url = {https://doi.org/10.1109/VTS.2012.6231098}, year = 2012 }
  Link
  https://doi.org/10.1109/VTS.2012.6231098
32. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerCBP12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233027}, pages = {1--6}, title = {On the quality of test vectors for post-silicon characterization}, url = {https://doi.org/10.1109/ETS.2012.6233027}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233027
2011
1. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianH11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2010.120}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {54--63}, title = {Selective Hardening: Toward Cost-Effective Error Tolerance}, url = {https://doi.org/10.1109/MDT.2010.120}, volume = 28, year = 2011 }
  Link
  https://doi.org/10.1109/MDT.2010.120
2. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tdsc/PolianHRB11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P. and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TDSC.2010.26}, journal = {{IEEE} Trans. Dependable Sec. Comput.}, number = 4, pages = {537--547}, title = {Modeling and Mitigating Transient Errors in Logic Circuits}, url = {https://doi.org/10.1109/TDSC.2010.26}, volume = 8, year = 2011 }
  Link
  https://doi.org/10.1109/TDSC.2010.26
3. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerTMLSPBB11, abteilung = {hocos}, author = {Sauer, Matthias and Tomashevich, Victor and M{\"{u}}ller, J{\"{o}}rg and Lewis, Matthew D. T. and Spilla, Andreas and Polian, Ilia and Becker, Bernd and Burgard, Wolfram}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993836}, pages = {182--185}, title = {An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors}, url = {https://doi.org/10.1109/IOLTS.2011.5993836}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993836
4. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianBHWM11, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Hellebrand, Sybille and Wunderlich, Hans{-}Joachim and Maxwell, Peter C.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.51}, pages = {219--225}, title = {Towards Variation-Aware Test Methods}, url = {https://doi.org/10.1109/ETS.2011.51}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.51
5. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PalerAPH11, abteilung = {hocos}, author = {Paler, Alexandru and Alaghi, Armin and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.43}, pages = {63--68}, title = {Tomographic Testing and Validation of Probabilistic Circuits}, url = {https://doi.org/10.1109/ETS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.43
6. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/SauerCSHPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2011, Cottbus, Germany, April 13-15, 2011}, crossref = {DBLP:conf/ddecs/2011}, doi = {10.1109/DDECS.2011.5783055}, pages = {93--98}, title = {SAT-based analysis of sensitisable paths}, url = {https://doi.org/10.1109/DDECS.2011.5783055}, year = 2011 }
  Link
  https://doi.org/10.1109/DDECS.2011.5783055
7. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993819}, pages = {104--110}, title = {Estimation of component criticality in early design steps}, url = {https://doi.org/10.1109/IOLTS.2011.5993819}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993819
8. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tdsc/PolianHRB11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P. and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TDSC.2010.26}, journal = {{IEEE} Trans. Dependable Sec. Comput.}, number = 4, pages = {537--547}, title = {Modeling and Mitigating Transient Errors in Logic Circuits}, url = {https://doi.org/10.1109/TDSC.2010.26}, volume = 8, year = 2011 }
  Link
  https://doi.org/10.1109/TDSC.2010.26
9. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/SauerCSHPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2011, Cottbus, Germany, April 13-15, 2011}, crossref = {DBLP:conf/ddecs/2011}, doi = {10.1109/DDECS.2011.5783055}, pages = {93--98}, title = {SAT-based analysis of sensitisable paths}, url = {https://doi.org/10.1109/DDECS.2011.5783055}, year = 2011 }
  Link
  https://doi.org/10.1109/DDECS.2011.5783055
10. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KrauseP11, abteilung = {hocos}, author = {Krause, Philipp Klaus and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France, March 14-18, 2011}, crossref = {DBLP:conf/date/2011}, doi = {10.1109/DATE.2011.5763153}, pages = {944--949}, title = {Adaptive voltage over-scaling for resilient applications}, url = {https://doi.org/10.1109/DATE.2011.5763153}, year = 2011 }
  Link
  https://doi.org/10.1109/DATE.2011.5763153
11. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter Maxwell. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
  Zusammenfassung
  Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.
  BibTeX
  @inproceedings{PoliaBHWM2011, abstract = {Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.}, abteilung = {ra}, address = {Trondheim, Norway}, author = {Polian, Ilia and Becker, Bernd and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Maxwell, Peter}, booktitle = {Proceedings of the 16th IEEE European Test Symposium (ETS'11)}, day = {23--27}, doi = {10.1109/ETS.2011.51}, isbn = {978-1-4577-0483-3}, issn = {1530-1877}, language = {English}, location = {Trondheim, Norway}, month = {05}, owner = {Thomas}, pages = {219--225}, project = {NotAck}, publisher = {IEEE Computer Society}, title = {{Towards Variation-Aware Test Methods}}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/ETS_PoliaBHWM2011.pdf}, year = 2011 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/ETS_PoliaBHWM2011.pdf
12. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New Delhi, India, November 20-23, 2011}, crossref = {DBLP:conf/ats/2011}, doi = {10.1109/ATS.2011.43}, pages = {108--113}, title = {Efficient SAT-Based Search for Longest Sensitisable Paths}, url = {https://doi.org/10.1109/ATS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ATS.2011.43
13. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (September 2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology.
  BibTeX
  @article{HopscBHPSVW2011, abstract = {To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology.}, abteilung = {ra}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, doi = {10.1007/s11432-011-4367-8}, file = {Article:/fileadmin/rami/files/publications/2011/SCIS_HopscBHPSVW2011.pdf}, issn = {1674-733X}, journal = {SCIENCE CHINA Information Sciences}, language = {English}, month = {09}, number = 9, owner = {Thomas}, pages = {1813--1826}, project = {REALTEST}, publisher = {Science China Press, co-published with Springer-Verlag}, title = {{Variation-Aware Fault Modeling}}, volume = 54, year = 2011 }
14. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianBHWM11, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Hellebrand, Sybille and Wunderlich, Hans{-}Joachim and Maxwell, Peter C.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.51}, pages = {219--225}, title = {Towards Variation-Aware Test Methods}, url = {https://doi.org/10.1109/ETS.2011.51}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.51
15. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter Maxwell. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
  Zusammenfassung
  Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.
  BibTeX
  @inproceedings{PoliaBHWM2011, abstract = {Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.}, abteilung = {ra}, address = {Trondheim, Norway}, author = {Polian, Ilia and Becker, Bernd and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Maxwell, Peter}, booktitle = {Proceedings of the 16th IEEE European Test Symposium (ETS'11)}, day = {23--27}, doi = {10.1109/ETS.2011.51}, isbn = {978-1-4577-0483-3}, issn = {1530-1877}, language = {English}, location = {Trondheim, Norway}, month = {05}, owner = {Thomas}, pages = {219--225}, project = {NotAck}, publisher = {IEEE Computer Society}, title = {{Towards Variation-Aware Test Methods}}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/ETS_PoliaBHWM2011.pdf}, year = 2011 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2011/ETS_PoliaBHWM2011.pdf
16. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New Delhi, India, November 20-23, 2011}, crossref = {DBLP:conf/ats/2011}, doi = {10.1109/ATS.2011.43}, pages = {108--113}, title = {Efficient SAT-Based Search for Longest Sensitisable Paths}, url = {https://doi.org/10.1109/ATS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ATS.2011.43
17. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerTMLSPBB11, abteilung = {hocos}, author = {Sauer, Matthias and Tomashevich, Victor and M{\"{u}}ller, J{\"{o}}rg and Lewis, Matthew D. T. and Spilla, Andreas and Polian, Ilia and Becker, Bernd and Burgard, Wolfram}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993836}, pages = {182--185}, title = {An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors}, url = {https://doi.org/10.1109/IOLTS.2011.5993836}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993836
18. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KrauseP11, abteilung = {hocos}, author = {Krause, Philipp Klaus and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France, March 14-18, 2011}, crossref = {DBLP:conf/date/2011}, doi = {10.1109/DATE.2011.5763153}, pages = {944--949}, title = {Adaptive voltage over-scaling for resilient applications}, url = {https://doi.org/10.1109/DATE.2011.5763153}, year = 2011 }
  Link
  https://doi.org/10.1109/DATE.2011.5763153
19. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993819}, pages = {104--110}, title = {Estimation of component criticality in early design steps}, url = {https://doi.org/10.1109/IOLTS.2011.5993819}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993819
20. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianH11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2010.120}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {54--63}, title = {Selective Hardening: Toward Cost-Effective Error Tolerance}, url = {https://doi.org/10.1109/MDT.2010.120}, volume = 28, year = 2011 }
  Link
  https://doi.org/10.1109/MDT.2010.120
21. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/chinaf/HopschBHPSVW11, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s11432-011-4367-8}, journal = {{SCIENCE} {CHINA} Information Sciences}, number = 9, pages = {1813--1826}, title = {Variation-aware fault modeling}, url = {https://doi.org/10.1007/s11432-011-4367-8}, volume = 54, year = 2011 }
  Link
  https://doi.org/10.1007/s11432-011-4367-8
22. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (September 2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  - Zusammenfassung
  - BibTeX
  Zusammenfassung
  To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology.
  BibTeX
  @article{HopscBHPSVW2011, abstract = {To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology.}, abteilung = {ra}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, doi = {10.1007/s11432-011-4367-8}, file = {Article:/fileadmin/rami/files/publications/2011/SCIS_HopscBHPSVW2011.pdf}, issn = {1674-733X}, journal = {SCIENCE CHINA Information Sciences}, language = {English}, month = {09}, number = 9, owner = {Thomas}, pages = {1813--1826}, project = {REALTEST}, publisher = {Science China Press, co-published with Springer-Verlag}, title = {{Variation-Aware Fault Modeling}}, volume = 54, year = 2011 }
23. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PalerAPH11, abteilung = {hocos}, author = {Paler, Alexandru and Alaghi, Armin and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.43}, pages = {63--68}, title = {Tomographic Testing and Validation of Probabilistic Circuits}, url = {https://doi.org/10.1109/ETS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.43
24. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/chinaf/HopschBHPSVW11, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s11432-011-4367-8}, journal = {{SCIENCE} {CHINA} Information Sciences}, number = 9, pages = {1813--1826}, title = {Variation-aware fault modeling}, url = {https://doi.org/10.1007/s11432-011-4367-8}, volume = 54, year = 2011 }
  Link
  https://doi.org/10.1007/s11432-011-4367-8
2010
1. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
  Zusammenfassung
  Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.
  BibTeX
  @incollection{BeckeP2010, abstract = {Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.}, abteilung = {hocos}, address = {Dordrecht}, author = {Becker, Bernd and Polian, Ilia}, booktitle = {Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault}, doi = {10.1007/978-90-481-3282-9_4}, issn = {978-90-481-3282-9}, owner = {haefneht}, pages = {105--131}, publisher = {Springer Netherlands}, refid = {Becker2010}, title = {Fault Modeling for Simulation and ATPG}, url = {https://doi.org/10.1007/978-90-481-3282-9_4}, year = 2010 }
  Link
  https://doi.org/10.1007/978-90-481-3282-9_4
2. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/BeckerHPSVW10, abteilung = {hocos}, author = {Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE/IFIP} International Conference on Dependable Systems and Networks Workshops {(DSN-W} 2010), Chicago, Illinois, USA, June 28 - July 1, 2010.}, crossref = {DBLP:conf/dsn/2010w}, doi = {10.1109/DSNW.2010.5542612}, pages = {95--100}, title = {Massive statistical process variations: {A} grand challenge for testing nanoelectronic circuits}, url = {https://doi.org/10.1109/DSNW.2010.5542612}, year = 2010 }
  Link
  https://doi.org/10.1109/DSNW.2010.5542612
3. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2010}, doi = {10.1109/VTS.2010.5469594}, pages = 130, title = {Special session 4B: Panel low-power test and noise-aware test: Foes or friends?}, url = {https://doi.org/10.1109/VTS.2010.5469594}, year = 2010 }
  Link
  https://doi.org/10.1109/VTS.2010.5469594
4. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewdts/PolianH10, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2010 East-West Design {\&} Test Symposium, {EWDTS} 2010, St. Petersburg, Russia, September 17-20, 2010}, crossref = {DBLP:conf/ewdts/2010}, doi = {10.1109/EWDTS.2010.5742135}, pages = {376--381}, title = {Advanced modeling of faults in Reversible circuits}, url = {https://doi.org/10.1109/EWDTS.2010.5742135}, year = 2010 }
  Link
  https://doi.org/10.1109/EWDTS.2010.5742135
5. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
  Zusammenfassung
  To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation- aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defectoriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defectfree case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.
  BibTeX
  @inproceedings{HopscBHPSVW2010, abstract = {To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation- aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defectoriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defectfree case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.}, abteilung = {ra}, address = {Shanghai, China}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the IEEE 19th Asian Test Symposium (ATS'10)}, day = {1--4}, doi = {10.1109/ATS.2010.24}, isbn = {978-0-7695-4248-5}, issn = {1081-7735}, language = {English}, location = {Shanghai, China}, month = {12}, owner = {Thomas}, pages = {87--93}, publisher = {IEEE Computer Society}, title = {{Variation-Aware Fault Modeling}}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ATS_HopscBHPSVW2010.pdf}, year = 2010 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ATS_HopscBHPSVW2010.pdf
6. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2010}, doi = {10.1109/VTS.2010.5469594}, pages = 130, title = {Special session 4B: Panel low-power test and noise-aware test: Foes or friends?}, url = {https://doi.org/10.1109/VTS.2010.5469594}, year = 2010 }
  Link
  https://doi.org/10.1109/VTS.2010.5469594
7. Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W’10), Chicago, Illinois, USA, 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
  Zusammenfassung
  Increasing parameter variations, high defect densities and a growing susceptibility to external noise in nanoscale technologies have led to a paradigm shift in design. Classical design strategies based on worst-case or average assumptions have been replaced by statistical design, and new robust and variation tolerant architectures have been developed. At the same time testing has become extremely challenging, as parameter variations may lead to an unacceptable behavior or change the impact of defects. Furthermore, for robust designs a precise quality assessment is required particularly showing the remaining robustness in the presence of manufacturing defects. The paper pinpoints the key challenges for testing nanoelectronic circuits in more detail, covering the range of variation-aware fault modeling via methods for statiscal testing and their algorithmic foundations to robustness analysis and quality binning.
  BibTeX
  @inproceedings{BeckeHPSVW2010, abstract = {Increasing parameter variations, high defect densities and a growing susceptibility to external noise in nanoscale technologies have led to a paradigm shift in design. Classical design strategies based on worst-case or average assumptions have been replaced by statistical design, and new robust and variation tolerant architectures have been developed. At the same time testing has become extremely challenging, as parameter variations may lead to an unacceptable behavior or change the impact of defects. Furthermore, for robust designs a precise quality assessment is required particularly showing the remaining robustness in the presence of manufacturing defects. The paper pinpoints the key challenges for testing nanoelectronic circuits in more detail, covering the range of variation-aware fault modeling via methods for statiscal testing and their algorithmic foundations to robustness analysis and quality binning.}, abteilung = {ra}, address = {Chicago, Illinois, USA}, author = {Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W'10)}, day = {28 June--1 July}, doi = {10.1109/DSNW.2010.5542612}, isbn = {978-1-4244-7729-6}, language = {English}, location = {Chicago, Illinois, USA}, owner = {Thomas}, pages = {95--100}, publisher = {IEEE Computer Society}, title = {{Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits}}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/WDSN_BeckerHPSVW2010.pdf}, year = 2010 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/WDSN_BeckerHPSVW2010.pdf
8. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jolpe/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1166/jolpe.2010.1075}, journal = {J. Low Power Electronics}, number = 2, pages = {326--338}, title = {Power Supply Noise: Causes, Effects, and Testing}, url = {https://doi.org/10.1166/jolpe.2010.1075}, volume = 6, year = 2010 }
  Link
  https://doi.org/10.1166/jolpe.2010.1075
9. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/BeckerHPSVW10, abteilung = {hocos}, author = {Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE/IFIP} International Conference on Dependable Systems and Networks Workshops {(DSN-W} 2010), Chicago, Illinois, USA, June 28 - July 1, 2010.}, crossref = {DBLP:conf/dsn/2010w}, doi = {10.1109/DSNW.2010.5542612}, pages = {95--100}, title = {Massive statistical process variations: {A} grand challenge for testing nanoelectronic circuits}, url = {https://doi.org/10.1109/DSNW.2010.5542612}, year = 2010 }
  Link
  https://doi.org/10.1109/DSNW.2010.5542612
10. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/HopschBHPSVW10, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4 December 2010, Shanghai, China}, crossref = {DBLP:conf/ats/2010}, doi = {10.1109/ATS.2010.24}, pages = {87--93}, title = {Variation-Aware Fault Modeling}, url = {https://doi.org/10.1109/ATS.2010.24}, year = 2010 }
  Link
  https://doi.org/10.1109/ATS.2010.24
11. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewdts/PolianH10, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2010 East-West Design {\&} Test Symposium, {EWDTS} 2010, St. Petersburg, Russia, September 17-20, 2010}, crossref = {DBLP:conf/ewdts/2010}, doi = {10.1109/EWDTS.2010.5742135}, pages = {376--381}, title = {Advanced modeling of faults in Reversible circuits}, url = {https://doi.org/10.1109/EWDTS.2010.5742135}, year = 2010 }
  Link
  https://doi.org/10.1109/EWDTS.2010.5742135
12. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/PolianB10, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1524/itit.2010.0590}, journal = {it - Information Technology}, number = 4, pages = {189--194}, title = {Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen f{\"{u}}r Nanoscale-Technologien)}, url = {https://doi.org/10.1524/itit.2010.0590}, volume = 52, year = 2010 }
  Link
  https://doi.org/10.1524/itit.2010.0590
13. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/ijpp/CzutroPLERB10, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10766-009-0124-7}, journal = {International Journal of Parallel Programming}, number = {3-4}, pages = {185--202}, title = {Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis}, url = {https://doi.org/10.1007/s10766-009-0124-7}, volume = 38, year = 2010 }
  Link
  https://doi.org/10.1007/s10766-009-0124-7
14. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
  Zusammenfassung
  Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.
  BibTeX
  @incollection{BeckeP2010, abstract = {Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.}, abteilung = {hocos}, address = {Dordrecht}, author = {Becker, Bernd and Polian, Ilia}, booktitle = {Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault}, doi = {10.1007/978-90-481-3282-9_4}, issn = {978-90-481-3282-9}, owner = {haefneht}, pages = {105--131}, publisher = {Springer Netherlands}, refid = {Becker2010}, title = {Fault Modeling for Simulation and ATPG}, url = {https://doi.org/10.1007/978-90-481-3282-9_4}, year = 2010 }
  Link
  https://doi.org/10.1007/978-90-481-3282-9_4
15. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/ijpp/CzutroPLERB10, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10766-009-0124-7}, journal = {International Journal of Parallel Programming}, number = {3-4}, pages = {185--202}, title = {Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis}, url = {https://doi.org/10.1007/s10766-009-0124-7}, volume = 38, year = 2010 }
  Link
  https://doi.org/10.1007/s10766-009-0124-7
16. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/PolianB10, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1524/itit.2010.0590}, journal = {it - Information Technology}, number = 4, pages = {189--194}, title = {Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen f{\"{u}}r Nanoscale-Technologien)}, url = {https://doi.org/10.1524/itit.2010.0590}, volume = 52, year = 2010 }
  Link
  https://doi.org/10.1524/itit.2010.0590
17. Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W’10), Chicago, Illinois, USA, 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
  Zusammenfassung
  Increasing parameter variations, high defect densities and a growing susceptibility to external noise in nanoscale technologies have led to a paradigm shift in design. Classical design strategies based on worst-case or average assumptions have been replaced by statistical design, and new robust and variation tolerant architectures have been developed. At the same time testing has become extremely challenging, as parameter variations may lead to an unacceptable behavior or change the impact of defects. Furthermore, for robust designs a precise quality assessment is required particularly showing the remaining robustness in the presence of manufacturing defects. The paper pinpoints the key challenges for testing nanoelectronic circuits in more detail, covering the range of variation-aware fault modeling via methods for statiscal testing and their algorithmic foundations to robustness analysis and quality binning.
  BibTeX
  @inproceedings{BeckeHPSVW2010, abstract = {Increasing parameter variations, high defect densities and a growing susceptibility to external noise in nanoscale technologies have led to a paradigm shift in design. Classical design strategies based on worst-case or average assumptions have been replaced by statistical design, and new robust and variation tolerant architectures have been developed. At the same time testing has become extremely challenging, as parameter variations may lead to an unacceptable behavior or change the impact of defects. Furthermore, for robust designs a precise quality assessment is required particularly showing the remaining robustness in the presence of manufacturing defects. The paper pinpoints the key challenges for testing nanoelectronic circuits in more detail, covering the range of variation-aware fault modeling via methods for statiscal testing and their algorithmic foundations to robustness analysis and quality binning.}, abteilung = {ra}, address = {Chicago, Illinois, USA}, author = {Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W'10)}, day = {28 June--1 July}, doi = {10.1109/DSNW.2010.5542612}, isbn = {978-1-4244-7729-6}, language = {English}, location = {Chicago, Illinois, USA}, owner = {Thomas}, pages = {95--100}, publisher = {IEEE Computer Society}, title = {{Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits}}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/WDSN_BeckerHPSVW2010.pdf}, year = 2010 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/WDSN_BeckerHPSVW2010.pdf
18. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/HopschBHPSVW10, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4 December 2010, Shanghai, China}, crossref = {DBLP:conf/ats/2010}, doi = {10.1109/ATS.2010.24}, pages = {87--93}, title = {Variation-Aware Fault Modeling}, url = {https://doi.org/10.1109/ATS.2010.24}, year = 2010 }
  Link
  https://doi.org/10.1109/ATS.2010.24
19. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jolpe/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1166/jolpe.2010.1075}, journal = {J. Low Power Electronics}, number = 2, pages = {326--338}, title = {Power Supply Noise: Causes, Effects, and Testing}, url = {https://doi.org/10.1166/jolpe.2010.1075}, volume = 6, year = 2010 }
  Link
  https://doi.org/10.1166/jolpe.2010.1075
20. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
  Zusammenfassung
  To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation- aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defectoriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defectfree case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.
  BibTeX
  @inproceedings{HopscBHPSVW2010, abstract = {To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation- aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defectoriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defectfree case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.}, abteilung = {ra}, address = {Shanghai, China}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the IEEE 19th Asian Test Symposium (ATS'10)}, day = {1--4}, doi = {10.1109/ATS.2010.24}, isbn = {978-0-7695-4248-5}, issn = {1081-7735}, language = {English}, location = {Shanghai, China}, month = {12}, owner = {Thomas}, pages = {87--93}, publisher = {IEEE Computer Society}, title = {{Variation-Aware Fault Modeling}}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ATS_HopscBHPSVW2010.pdf}, year = 2010 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2010/ATS_HopscBHPSVW2010.pdf
2009
1. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/HungerHCPB09, abteilung = {hocos}, author = {Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {15th {IEEE} International On-Line Testing Symposium {(IOLTS} 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal}, crossref = {DBLP:conf/iolts/2009}, doi = {10.1109/IOLTS.2009.5196027}, pages = {269--274}, title = {ATPG-based grading of strong fault-secureness}, url = {https://doi.org/10.1109/IOLTS.2009.5196027}, year = 2009 }
  Link
  https://doi.org/10.1109/IOLTS.2009.5196027
2. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/todaes/EngelkeBRSBP09, abteilung = {hocos}, author = {Engelke, Piet and Becker, Bernd and Renovell, Michel and Schl{\"{o}}ffel, J{\"{u}}rgen and Braitling, Bettina and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/1562514.1596831}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, number = 4, pages = {56:1--56:21}, title = {{SUPERB:} Simulator utilizing parallel evaluation of resistive bridges}, url = {https://doi.org/10.1145/1562514.1596831}, volume = 14, year = 2009 }
  Link
  https://doi.org/10.1145/1562514.1596831
3. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/HungerHCPB09, abteilung = {hocos}, author = {Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {15th {IEEE} International On-Line Testing Symposium {(IOLTS} 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal}, crossref = {DBLP:conf/iolts/2009}, doi = {10.1109/IOLTS.2009.5196027}, pages = {269--274}, title = {ATPG-based grading of strong fault-secureness}, url = {https://doi.org/10.1109/IOLTS.2009.5196027}, year = 2009 }
  Link
  https://doi.org/10.1109/IOLTS.2009.5196027
4. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroPLERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on {VLSI} Design, New Delhi, India, 5-9 January 2009}, crossref = {DBLP:conf/vlsid/2009}, doi = {10.1109/VLSI.Design.2009.20}, pages = {227--232}, title = {{TIGUAN:} Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis}, url = {https://doi.org/10.1109/VLSI.Design.2009.20}, year = 2009 }
  Link
  https://doi.org/10.1109/VLSI.Design.2009.20
5. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/glvlsi/GaneshpurePKB09, abteilung = {hocos}, author = {Ganeshpure, Kunal P. and Polian, Ilia and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009, Boston Area, MA, USA, May 10-12 2009}, crossref = {DBLP:conf/glvlsi/2009}, doi = {10.1145/1531542.1531560}, pages = {63--68}, title = {Reducing temperature variability by routing heat pipes}, url = {https://doi.org/10.1145/1531542.1531560}, year = 2009 }
  Link
  https://doi.org/10.1145/1531542.1531560
6. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/HouarcheCRCEPB09, abteilung = {hocos}, author = {Houarche, Nicolas and Comte, Mariane and Renovell, Michel and Czutro, Alejandro and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2009}, doi = {10.1109/VTS.2009.57}, pages = {21--26}, title = {An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects}, url = {https://doi.org/10.1109/VTS.2009.57}, year = 2009 }
  Link
  https://doi.org/10.1109/VTS.2009.57
7. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/IzosimovPPEP09, abteilung = {hocos}, author = {Izosimov, Viacheslav and Polian, Ilia and Pop, Paul and Eles, Petru and Peng, Zebo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France, April 20-24, 2009}, crossref = {DBLP:conf/date/2009}, doi = {10.1109/DATE.2009.5090752}, pages = {682--687}, title = {Analysis and optimization of fault-tolerant embedded systems with hardened processors}, url = {https://doi.org/10.1109/DATE.2009.5090752}, year = 2009 }
  Link
  https://doi.org/10.1109/DATE.2009.5090752
8. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroPERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26 November 2009, Taichung, Taiwan}, crossref = {DBLP:conf/ats/2009}, doi = {10.1109/ATS.2009.31}, pages = {187--190}, title = {Dynamic Compaction in SAT-Based {ATPG}}, url = {https://doi.org/10.1109/ATS.2009.31}, year = 2009 }
  Link
  https://doi.org/10.1109/ATS.2009.31
9. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/glvlsi/GaneshpurePKB09, abteilung = {hocos}, author = {Ganeshpure, Kunal P. and Polian, Ilia and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009, Boston Area, MA, USA, May 10-12 2009}, crossref = {DBLP:conf/glvlsi/2009}, doi = {10.1145/1531542.1531560}, pages = {63--68}, title = {Reducing temperature variability by routing heat pipes}, url = {https://doi.org/10.1145/1531542.1531560}, year = 2009 }
  Link
  https://doi.org/10.1145/1531542.1531560
10. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroPERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26 November 2009, Taichung, Taiwan}, crossref = {DBLP:conf/ats/2009}, doi = {10.1109/ATS.2009.31}, pages = {187--190}, title = {Dynamic Compaction in SAT-Based {ATPG}}, url = {https://doi.org/10.1109/ATS.2009.31}, year = 2009 }
  Link
  https://doi.org/10.1109/ATS.2009.31
11. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/IzosimovPPEP09, abteilung = {hocos}, author = {Izosimov, Viacheslav and Polian, Ilia and Pop, Paul and Eles, Petru and Peng, Zebo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France, April 20-24, 2009}, crossref = {DBLP:conf/date/2009}, doi = {10.1109/DATE.2009.5090752}, pages = {682--687}, title = {Analysis and optimization of fault-tolerant embedded systems with hardened processors}, url = {https://doi.org/10.1109/DATE.2009.5090752}, year = 2009 }
  Link
  https://doi.org/10.1109/DATE.2009.5090752
12. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/todaes/EngelkeBRSBP09, abteilung = {hocos}, author = {Engelke, Piet and Becker, Bernd and Renovell, Michel and Schl{\"{o}}ffel, J{\"{u}}rgen and Braitling, Bettina and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/1562514.1596831}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, number = 4, pages = {56:1--56:21}, title = {{SUPERB:} Simulator utilizing parallel evaluation of resistive bridges}, url = {https://doi.org/10.1145/1562514.1596831}, volume = 14, year = 2009 }
  Link
  https://doi.org/10.1145/1562514.1596831
13. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/HouarcheCRCEPB09, abteilung = {hocos}, author = {Houarche, Nicolas and Comte, Mariane and Renovell, Michel and Czutro, Alejandro and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2009}, doi = {10.1109/VTS.2009.57}, pages = {21--26}, title = {An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects}, url = {https://doi.org/10.1109/VTS.2009.57}, year = 2009 }
  Link
  https://doi.org/10.1109/VTS.2009.57
14. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroPLERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on {VLSI} Design, New Delhi, India, 5-9 January 2009}, crossref = {DBLP:conf/vlsid/2009}, doi = {10.1109/VLSI.Design.2009.20}, pages = {227--232}, title = {{TIGUAN:} Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis}, url = {https://doi.org/10.1109/VLSI.Design.2009.20}, year = 2009 }
  Link
  https://doi.org/10.1109/VLSI.Design.2009.20
2008
1. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianMNKEBSW08, abteilung = {hocos}, author = {Polian, Ilia and Miyase, Kohei and Nakamura, Yusuke and Kajihara, Seiji and Engelke, Piet and Becker, Bernd and Spinner, Stefan and Wen, Xiaoqing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 11th {IEEE} Workshop on Design {\&} Diagnostics of Electronic Circuits {\&} Systems {(DDECS} 2008), Bratislava, Slovakia, April 16-18, 2008}, crossref = {DBLP:conf/ddecs/2008}, doi = {10.1109/DDECS.2008.4538798}, pages = {263--266}, title = {Diagnosis of Realistic Defects Based on the X-Fault Model}, url = {https://doi.org/10.1109/DDECS.2008.4538798}, year = 2008 }
  Link
  https://doi.org/10.1109/DDECS.2008.4538798
2. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In Proceedings of the 13th IEEE European Test Symposium (ETS’08), Lago Maggiore, Italy, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
  Zusammenfassung
  Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.
  BibTeX
  @inproceedings{ZoellWPB2008, abstract = {Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.}, abteilung = {ra}, author = {Zoellin, Christian G. and Wunderlich, Hans-Joachim and Polian, Ilia and Becker, Bernd}, booktitle = {Proceedings of the 13th IEEE European Test Symposium (ETS'08)}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {25--29}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/ETS.2008.30}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-0-7695-3150-2}, issn = {1530-1877}, language = {English}, location = {Lago Maggiore, Italy}, month = {05}, owner = {Thomas}, pages = {185--190}, project = {DFG460 ; REALTEST}, publisher = {IEEE Computer Society}, title = {{Selective Hardening in Early Design Steps}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/ETS_ZoellWPB2008.pdf}, year = 2008 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/ETS_ZoellWPB2008.pdf
3. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroHEPCRB08, abteilung = {hocos}, author = {Czutro, Alejandro and Houarche, Nicolas and Engelke, Piet and Polian, Ilia and Comte, Mariane and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.19}, pages = {113--118}, title = {A Simulator of Small-Delay Faults Caused by Resistive-Open Defects}, url = {https://doi.org/10.1109/ETS.2008.19}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.19
4. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/SpinnerPEBKC08, abteilung = {hocos}, author = {Spinner, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {26th {IEEE} {VLSI} Test Symposium {(VTS} 2008), April 27 - May 1, 2008, San Diego, California, {USA}}, crossref = {DBLP:conf/vts/2008}, doi = {10.1109/VTS.2008.30}, pages = {181--186}, title = {Automatic Test Pattern Generation for Interconnect Open Defects}, url = {https://doi.org/10.1109/VTS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/VTS.2008.30
5. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/ZoellinWPB08, abteilung = {hocos}, author = {Zoellin, Christian G. and Wunderlich, Hans{-}Joachim and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.30}, pages = {185--190}, title = {Selective Hardening in Early Design Steps}, url = {https://doi.org/10.1109/ETS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.30
6. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianR08, abteilung = {hocos}, author = {Polian, Ilia and Rao, Wenjing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.26}, pages = {263--271}, title = {Selective Hardening of NanoPLA Circuits}, url = {https://doi.org/10.1109/DFT.2008.26}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.26
7. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/isvlsi/PolianRB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9 April 2008, Montpellier, France}, crossref = {DBLP:conf/isvlsi/2008}, doi = {10.1109/ISVLSI.2008.22}, pages = {257--262}, title = {Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors}, url = {https://doi.org/10.1109/ISVLSI.2008.22}, year = 2008 }
  Link
  https://doi.org/10.1109/ISVLSI.2008.22
8. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/NowrothPB08, abteilung = {hocos}, author = {Nowroth, Damian and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {The 38th Annual {IEEE/IFIP} International Conference on Dependable Systems and Networks, {DSN} 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings}, crossref = {DBLP:conf/dsn/2008}, doi = {10.1109/DSN.2008.4630068}, pages = {32--41}, title = {A study of cognitive resilience in a {JPEG} compressor}, url = {https://doi.org/10.1109/DSN.2008.4630068}, year = 2008 }
  Link
  https://doi.org/10.1109/DSN.2008.4630068
9. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/SpinnerPEBKC08, abteilung = {hocos}, author = {Spinner, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {26th {IEEE} {VLSI} Test Symposium {(VTS} 2008), April 27 - May 1, 2008, San Diego, California, {USA}}, crossref = {DBLP:conf/vts/2008}, doi = {10.1109/VTS.2008.30}, pages = {181--186}, title = {Automatic Test Pattern Generation for Interconnect Open Defects}, url = {https://doi.org/10.1109/VTS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/VTS.2008.30
10. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/EngelkePRKSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Kundu, Sandip and Seshadri, Bharath and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2007.913382}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 2, pages = {327--338}, title = {On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing}, url = {https://doi.org/10.1109/TCAD.2007.913382}, volume = 27, year = 2008 }
  Link
  https://doi.org/10.1109/TCAD.2007.913382
11. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/isvlsi/PolianRB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9 April 2008, Montpellier, France}, crossref = {DBLP:conf/isvlsi/2008}, doi = {10.1109/ISVLSI.2008.22}, pages = {257--262}, title = {Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors}, url = {https://doi.org/10.1109/ISVLSI.2008.22}, year = 2008 }
  Link
  https://doi.org/10.1109/ISVLSI.2008.22
12. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianR08, abteilung = {hocos}, author = {Polian, Ilia and Rao, Wenjing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.26}, pages = {263--271}, title = {Selective Hardening of NanoPLA Circuits}, url = {https://doi.org/10.1109/DFT.2008.26}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.26
13. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianRPTB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Pomeranz, Irith and Tang, Xun and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.20}, pages = {245--253}, title = {On Reducing Circuit Malfunctions Caused by Soft Errors}, url = {https://doi.org/10.1109/DFT.2008.20}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.20
14. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/HillebrechtPEBKC08, abteilung = {hocos}, author = {Hillebrecht, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara, California, USA, October 26-31, 2008}, crossref = {DBLP:conf/itc/2008}, doi = {10.1109/TEST.2008.4700642}, pages = {1--10}, title = {Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model}, url = {https://doi.org/10.1109/TEST.2008.4700642}, year = 2008 }
  Link
  https://doi.org/10.1109/TEST.2008.4700642
15. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/EngelkePSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Schl{\"{o}}ffel, J{\"{u}}rgen and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany, March 10-14, 2008}, crossref = {DBLP:conf/date/2008}, doi = {10.1109/DATE.2008.4484747}, pages = {628--633}, title = {Resistive Bridging Fault Simulation of Industrial Circuits}, url = {https://doi.org/10.1109/DATE.2008.4484747}, year = 2008 }
  Link
  https://doi.org/10.1109/DATE.2008.4484747
16. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianMNKEBSW08, abteilung = {hocos}, author = {Polian, Ilia and Miyase, Kohei and Nakamura, Yusuke and Kajihara, Seiji and Engelke, Piet and Becker, Bernd and Spinner, Stefan and Wen, Xiaoqing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 11th {IEEE} Workshop on Design {\&} Diagnostics of Electronic Circuits {\&} Systems {(DDECS} 2008), Bratislava, Slovakia, April 16-18, 2008}, crossref = {DBLP:conf/ddecs/2008}, doi = {10.1109/DDECS.2008.4538798}, pages = {263--266}, title = {Diagnosis of Realistic Defects Based on the X-Fault Model}, url = {https://doi.org/10.1109/DDECS.2008.4538798}, year = 2008 }
  Link
  https://doi.org/10.1109/DDECS.2008.4538798
17. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianRPTB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Pomeranz, Irith and Tang, Xun and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.20}, pages = {245--253}, title = {On Reducing Circuit Malfunctions Caused by Soft Errors}, url = {https://doi.org/10.1109/DFT.2008.20}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.20
18. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroHEPCRB08, abteilung = {hocos}, author = {Czutro, Alejandro and Houarche, Nicolas and Engelke, Piet and Polian, Ilia and Comte, Mariane and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.19}, pages = {113--118}, title = {A Simulator of Small-Delay Faults Caused by Resistive-Open Defects}, url = {https://doi.org/10.1109/ETS.2008.19}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.19
19. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/EngelkePRKSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Kundu, Sandip and Seshadri, Bharath and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2007.913382}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 2, pages = {327--338}, title = {On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing}, url = {https://doi.org/10.1109/TCAD.2007.913382}, volume = 27, year = 2008 }
  Link
  https://doi.org/10.1109/TCAD.2007.913382
20. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/EngelkePSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Schl{\"{o}}ffel, J{\"{u}}rgen and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany, March 10-14, 2008}, crossref = {DBLP:conf/date/2008}, doi = {10.1109/DATE.2008.4484747}, pages = {628--633}, title = {Resistive Bridging Fault Simulation of Industrial Circuits}, url = {https://doi.org/10.1109/DATE.2008.4484747}, year = 2008 }
  Link
  https://doi.org/10.1109/DATE.2008.4484747
21. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/HillebrechtPEBKC08, abteilung = {hocos}, author = {Hillebrecht, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara, California, USA, October 26-31, 2008}, crossref = {DBLP:conf/itc/2008}, doi = {10.1109/TEST.2008.4700642}, pages = {1--10}, title = {Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model}, url = {https://doi.org/10.1109/TEST.2008.4700642}, year = 2008 }
  Link
  https://doi.org/10.1109/TEST.2008.4700642
22. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In Proceedings of the 13th IEEE European Test Symposium (ETS’08), Lago Maggiore, Italy, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
  Zusammenfassung
  Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.
  BibTeX
  @inproceedings{ZoellWPB2008, abstract = {Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.}, abteilung = {ra}, author = {Zoellin, Christian G. and Wunderlich, Hans-Joachim and Polian, Ilia and Becker, Bernd}, booktitle = {Proceedings of the 13th IEEE European Test Symposium (ETS'08)}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {25--29}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/ETS.2008.30}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-0-7695-3150-2}, issn = {1530-1877}, language = {English}, location = {Lago Maggiore, Italy}, month = {05}, owner = {Thomas}, pages = {185--190}, project = {DFG460 ; REALTEST}, publisher = {IEEE Computer Society}, title = {{Selective Hardening in Early Design Steps}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/ETS_ZoellWPB2008.pdf}, year = 2008 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/ETS_ZoellWPB2008.pdf
23. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/NowrothPB08, abteilung = {hocos}, author = {Nowroth, Damian and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {The 38th Annual {IEEE/IFIP} International Conference on Dependable Systems and Networks, {DSN} 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings}, crossref = {DBLP:conf/dsn/2008}, doi = {10.1109/DSN.2008.4630068}, pages = {32--41}, title = {A study of cognitive resilience in a {JPEG} compressor}, url = {https://doi.org/10.1109/DSN.2008.4630068}, year = 2008 }
  Link
  https://doi.org/10.1109/DSN.2008.4630068
24. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/ZoellinWPB08, abteilung = {hocos}, author = {Zoellin, Christian G. and Wunderlich, Hans{-}Joachim and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.30}, pages = {185--190}, title = {Selective Hardening in Early Design Steps}, url = {https://doi.org/10.1109/ETS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.30
2007
1. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianCKB07, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2007.77}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {276--284}, title = {Power Droop Testing}, url = {https://doi.org/10.1109/MDT.2007.77}, volume = 24, year = 2007 }
  Link
  https://doi.org/10.1109/MDT.2007.77
2. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/corr/abs-0711-3289, abteilung = {hocos}, archiveprefix = {arXiv}, author = {Spinner, Stefan and Bartholomeyczik, J. and Becker, Bernd and Doelle, M. and Paul, Oliver and Polian, Ilia and Roth, R. and Seitz, K. and Ruther, Patrick}, bibsource = {dblp computer science bibliography, https://dblp.org}, eprint = {0711.3289}, journal = {CoRR}, title = {Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors}, url = {http://arxiv.org/abs/0711.3289}, volume = {abs/0711.3289}, year = 2007 }
  Link
  http://arxiv.org/abs/0711.3289
3. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianCKB07, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2007.77}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {276--284}, title = {Power Droop Testing}, url = {https://doi.org/10.1109/MDT.2007.77}, volume = 24, year = 2007 }
  Link
  https://doi.org/10.1109/MDT.2007.77
4. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/HayesPB07, abteilung = {hocos}, author = {Hayes, John P. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley, California, {USA}}, crossref = {DBLP:conf/vts/2007}, doi = {10.1109/VTS.2007.13}, pages = {249--255}, title = {An Analysis Framework for Transient-Error Tolerance}, url = {https://doi.org/10.1109/VTS.2007.13}, year = 2007 }
  Link
  https://doi.org/10.1109/VTS.2007.13
5. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianF07, abteilung = {hocos}, author = {Polian, Ilia and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-007-5013-7}, journal = {J. Electronic Testing}, number = 5, pages = {445--455}, title = {Functional Constraints vs. Test Compression in Scan-Based Delay Testing}, url = {https://doi.org/10.1007/s10836-007-5013-7}, volume = 23, year = 2007 }
  Link
  https://doi.org/10.1007/s10836-007-5013-7
6. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/PolianNB07, abteilung = {hocos}, author = {Polian, Ilia and Nowroth, Damian and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th {IEEE} International On-Line Testing Symposium {(IOLTS} 2007), 8-11 July 2007, Heraklion, Crete, Greece}, crossref = {DBLP:conf/iolts/2007}, doi = {10.1109/IOLTS.2007.38}, pages = {201--202}, title = {Identification of Critical Errors in Imaging Applications}, url = {https://doi.org/10.1109/IOLTS.2007.38}, year = 2007 }
  Link
  https://doi.org/10.1109/IOLTS.2007.38
7. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianF07, abteilung = {hocos}, author = {Polian, Ilia and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-007-5013-7}, journal = {J. Electronic Testing}, number = 5, pages = {445--455}, title = {Functional Constraints vs. Test Compression in Scan-Based Delay Testing}, url = {https://doi.org/10.1007/s10836-007-5013-7}, volume = 23, year = 2007 }
  Link
  https://doi.org/10.1007/s10836-007-5013-7

Lehre

Teaching and Advising

Graduate (Master-level) courses in Stuttgart: «Hardware-oriented Security», «Computer Architecture and Organization», «Electronic Design Automation», «Robust System Design», research-oriented seminars «Hardware-oriented Security», «Emerging Architectures»
Undergraduate (Bachelor-level) courses in Stuttgart: «Computer Organization I», «Computer Organization II» (practical)
Courses in Passau (before 2017): «Combinational and Sequential Circuits», «Computer Engineering», «Computer Architecture», «Embedded Systems» «Electronic Design Automation», «Robust System Design»
Courses in Freiburg (before 2010): «Computer Engineering», «Computer Architecture», «Embedded Systems», «Test and Reliability»

Teaching-oriented Functions and Contributions

Conceptualized and introduced new study program «Mobile and Embedded Systems» in Passau
Introduced an English-taught track of Master in Computer Science in Passau, which students without German-language skills can take (partially funded by StMWFK)
Head of the Examination Committee in Passau, 10/2010 – 09/2013
Pilot project on using e-Learning for student marketing in Passau

Current Doctoral Students in Stuttgart

Sebastian Brandhofer
Preliminary topic: Synthesis of Robust Quantum Computers
Mael Gay
Preliminary topic: Fault-injection Attacks and Countermeasures
Florian Neugebauer
Preliminary topic: Stochastic Circuits

Visiting Doctoral Students in Stuttgart

Felipe Valencia (August 2018 – July 2019)
Home institution: Universita della Svizzera Italiana, Lugano (advisor: F. Regazzoni)
Topic: Hardware Acceleration for Post-quantum Cryptography

Doctoral Students Supervised in Nassau

Jie Jiang (2010 – 2016)
Title: Delay Testing in Nanoscale Technology under Process Variations
Philipp Jovanovic (2011 – 2015, co-supervised by Prof. Martin Kreuzer, summa cum laude)
Title: Analysis and Design of Symmetric Cryptographic Algorithms Current employer: EPFL Lausanne
Josef Kinseher (2014 – 2018)
Title: New Methods for Improving Embedded Memory Manufacturing Tests Current employer: Intel Wireless, Munich
Alexandru Paler (2010 – 2014)
Title: Design Methods for Reliable Quantum Circuits Current employer: University of Linz
Victor Tomashevich (2010 – 2016)
Title: Fault Tolerance Aspects of Virtual Massive MIMO Systems

Visiting Doctoral Students in Passau

Raghavan Kumar (July – December 2013)
Home institution: University of Massachusetts, Amherst (advisor: Wayne P. Burleson)
Topic: Hardware Trojans for fault-based attacks
Sudarshan Srinivasan (July – December 2011)
Home institution: University of Massachusetts, Amherst (advisor: Sandip Kundu)
Topic: Cross-level protection against faults and attacks

Doctoral Students Co-Supervised in Freiburg (before 2010)

Piet Engelke (2003 – 2009, summa cum laude)
Title: Resistive bridging faults
Current employer: Infineon Technologies, Munich
Stefan Spinner (2005 – 2010, married and changed name to Hillebrecht in 2008)
Title: Interconnect reliability and test
Current employer: Advantest, Böblingen
Alexander Czutro (2007 – 2013)
Title: Efficiency and Applications of SAT-Based Test Pattern Generation – Complex fault models and optimisation problems
Current employer: Besi Switzerland AG
Matthias Sauer (2010 – 2013, summa cum laude)
Title: Testing time – time to test
Current employer: University of Freiburg
Philipp-Klaus Krause (2009 – 2010; moved to University of Frankfurt in 2010)
Topic: Adaptive voltage over-scaling

Lebenslauf

Brief Biography

Since 10/2017:	Full Professor and Director of ITI, University of Stuttgart, Germany
04/2010 – 10/2017:	Full Professor and Chair of Computer Engineering, University of Passau, Germany
10/2013 – 09/2015:	Dean of the Faculty of Computer Science and Mathematics, University of Passau, Germany
12/2008 – 03/2008:	Managing Director, Freiburg Centre for Security and Society
12/2003 – 03/2010:	Senior postdoctoral researcher (C1) and leader of the sub-group «test and reliability», Computer Architecture Group, University of Freiburg
10/1999 – 11/2003:	Researcher, Computer Architecture Group, University of Freiburg

Degrees

Diploma (MSc) 1999
Dr. rer. nat. (PhD; summa cum laude) 2003
Habilitation (professor's qualification exam) 2008,
all in Computer Science and from the University of Freiburg
Diploma in Economics (with distinction) from the University of Hagen 2008

Longer Research Visits and Internships

04/2016 – 07/2016:	FRIAS Fellow, Freiburg Institute of Advanced Studies, Freiburg, Germany
06/2012 – 07/2012:	Research visitor, University of Michigan, Ann Arbor, USA
05/2005 – 09/2005:	JSPS Visiting Research Fellow, Nara Institute of Science and Technology, Japan
07/1998 – 10/1998:	Intern, IBM Deutschland Entwicklung GmbH, Böblingen, Germany
10/1997 – 03/1998:	Intern, Micronas Intermetall, Freiburg

Awards

Best paper award, IEEE European Test Symposium 2014
Best paper award nomination, ACM/IEEE ASP-DAC Conference 2013
Best paper award in category «Test», IEEE DDECS Symposium 2011
Two papers (from 2004 and 2010) selected for the compendium volume «Best papers 2002–2011 of the IEEE Asian Test Symposium»
IEEE Senior Member (since 2007)
Ph.D. thesis proposed for German Informatics Society Outstanding Dissertation Award abstract published in «Outstanding Computer Science Dissertations 2003» by German Computer Science Society.
Wolfgang-Gentner Award 2004 for outstanding scientific performance of a young researcher (link in German; sponsored by Volksbank Freiburg; co-laureate with Felix Klädtke and Maren Bennewitz).
European Champion and Vice World Champion at ACM International Collegiate Programming Contest 1999 (final results and a report in a newspaper)
VDI Award 1999 (sponsored by VDI, the German Engineering Association; co-laureate with Immanuel Herrmann and Daniel Fleig)
Referent for foreign student affairs at AStA (Student Union); 1994-95
DAAD Award 1995 (sponsored by DAAD, the German Academic Exchange Program)

Awards and Recognitions Obtained by Students during my Supervision

Faculty Award for the best doctoral dissertation for Philipp Jovanovic (2016)
Authenticated stream cipher NORX by Philpp Jovanovic selected for the third round of the CAESAR competition (2015). Invited talk at 31C3 congress in Berlin.
Successful attack on the Open Smart Grid Protocol by Philipp Jovanovic
Wolfgang Gentner Award for outstanding doctoral thesis of Matthias Sauer. The thesis finishes second in the best thesis competition at IEEE European Test Symposium (2014)
Alexandru Paler invited to Heidelberg Laureate Forum (2013)
Piet Engelke wins the best thesis competition at IEEE European Test Symposium (2009)

Membership and Functions in Professional Organizations

Membership: IEEE (Senior Member since 2007), GI (German Informatics Society), DHV (German University Professors Association)
Student Activities Chair, Test Technology Technical Council (TTTC), IEEE Computer Society, 2010 – 2012
Worldwide coordinator of TTTC‘s E.J. McCluskey Best Doctoral Thesis Award (Annual contest of PhD graduates with thesis on test methods or reliability with semi-finals at regional IEEE symposia and finals at a major IEEE conference)
Program Chair of the TTTC Test Technology Educational Program (TTEP) since 2017
Vice Speaker of interest group 5 “test methods and reliability of circuits and systems” of joint committee RSS «computer-aided circuit and system design» of three national societies: GI (FA 3.5), VDE/VDI GMM (FB 8) and VDE ITG (FA 8.2) (since 2012)

Community Service

Conference Organization

Design Automation and Test in Europe Conference (DATE): Track Chair DT6 (Design and Test of Secure Systems) 2018 (Dresden), 2019 (Florence)
International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE): Program Chair 2019 (Darmstadt)
International Verification and Security Workshop (IVSW): Program Chair 2018 (Platja d’Aro), Special Session Chair 2017 (Thessaloniki)
Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE): Program Chair 2013 (Avignon), General Chair 2014 (Paderborn), 2015 (Grenoble)
IEEE European Test Symposium: Finance Chair 2007 (Freiburg), Student Forum / Student Activities Chair 2009 (Sevilla), 2011 (Trondheim), 2012 (Annecy); Fringe Workshop Chair 2013 (Avignon), 2014 (Paderborn); Topic Chair Automatic Test Pattern Generation 2015 (Cluj-Napoca), 2016 (Amsterdam), 2017 (Limassol), 2018 (Bremen); Topic Chair Hardware Security 2019 (Baden-Baden)
GI/ITG/GMM Workshop on Test Methods & Reliability (TUZ): General Chair 2011 (Passau), co-organizer 2006 (Freiburg)
IEEE Asian Test Symposium (ATS): European Liaison 2012 (Niigata)
IEEE RASDAT Workshop: Vice Program Chair 2010 (Bangalore), 2011 (Chennai), 2012 (Hyderabad)
South European Test Seminar: General Chair 2008 and 2013, (Obergurgl, Austria)

Program Committee Member

Past Program Committee Member

International Test Conference (ITC) 2012 (Anaheim), 2013 (Anaheim), 2014 (Seattle)
IEEE Asian Test Symposium (ATS) 2006 (Fukuoka), 2007 (Beijing), 2009 (Taichung, Taiwan), 2011 (New Delhi), 2012 (Niigata), 2013 (Yilan)
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2017 (Banff)
International Conference on VLSI Design (VLSID) 2012 (Hyderabad), 2014 (Mumbai)
International Symposium on VLSI Design and Test (VDAT) 2015 (Mumbai)
ACS Int’l Conf. on Advanced Computing and Communications (ADCOM) 2009 (Bangalore)
IFIP Workshop on Information Security: Theory and Practice (WISTP) 2012 (Egham, UK)
IEEE Workshop on RTL and high-level testing 2006 (Fukuoka), 2007 (Beijing), 2008 (Sapporo), 2011 (Jaipur), 2012 (Niigata), 2013 (Jaosi, Taiwan), 2016 (Hiroshima)
International Workshop on Impact of Low-Power design on Test and Reliability (LPonTR) 2009 (Sevilla), 2010 (Prague), 2011 (Trondheim), 2012 (Annecy)

Organization of Dagstuhl Seminars

Hardware Security (May 2016) – with Osnat Keren (Bar Ilan University, IL), Mark M. Tehranipoor (University of Florida, US), Pim Tuyls (Intrinsic-ID, BE)
Secure Composition for Hardware Systems (July 2019) – with Arora Divya (Intel, US), Francesco Regazzoni (USI Lugano, CH), Patrick Schaumont (Virginia Tech, US)

Other Service for Conferences and Journals

Guest Editor of the Special Issue on Hardware-oriented Security, it – Information Technology, 2019
Guest Editor of the Special Issue «Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels», Journal of Low Power and Applications (JLPEA), 2016
Guest Editor of the Special Issue on Hardware Security, IET Computers & Digital Techniques, 2014
Panel organizer or panelist: IEEE WRTLT 2007 (Hongkong), IEEE ETS 2007 (Freiburg), ITC 2008 (Santa Clara), IEEE RASDAT 2010 (Bangalore), IEEE VTS 2010 (Santa Cruz), IEEE RASDAT 2011 (Chennai), IEEE ETS 2013 (Avignon), IVSW 2016 (Sant Feliu de Guixols), FDTC 2017 (Taipeh), IVSW 2018 (Platja d'Aro)
Special Session Organizer: WDSN 2010 (Chicago), LPonTR 2010 (Prague), WDSN 2010 (Chicago), IEEE ATS 2010 (Shanghai), LPonTR 2011 (Trondheim), LPonTR 2012 (Annecy), IEEE ATS 2012 (Niigata), IEEE VTS 2013 (Berkeley), ACM/IEEE DAC 2015 (San Francisco), IEEE SOCC 2017 (Munich), ICCAD 2018 (San Diego)
Tutorial presenter: GI/ITG/GMM ZUE 2007 (Munich), LPonTR 2009 (Sevilla), IEEE DDECS 2013 (Karlowy Vary), TRUDEVICE Training School 2016 (Leukerbad)

Ilia Polian

Kontakt

Fachgebiet

Research Interests and Activities

Publikationen

2024

BibTeX

Link

BibTeX

2023

BibTeX

Zusammenfassung

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

Link

BibTeX

BibTeX

2022

BibTeX

BibTeX

BibTeX

BibTeX

Zusammenfassung

BibTeX

Link

BibTeX

BibTeX

Zusammenfassung

BibTeX

Link

Zusammenfassung

BibTeX

Link

BibTeX

BibTeX

2021

Zusammenfassung

BibTeX

BibTeX

Zusammenfassung

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

Zusammenfassung

BibTeX

Link

BibTeX

Link

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

BibTeX

2020

Zusammenfassung

BibTeX

BibTeX

Zusammenfassung

BibTeX

BibTeX

Zusammenfassung

BibTeX

Zusammenfassung

BibTeX